Red Semiconductor announces VISC extension to RISC-V
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Startup chip company Red Semiconductor Ltd. (Oxford, England) has announced VISC, its RISC-V based instruction set architecture with extensions for edge AI and cryptography.
VISC stands for Versatile Intrinsic Structured Computing. It is an accelerated RISC-V microprocessor core that supports mathematical algorithms for parallel execution in its reconfiguration hardware engine. The company claims VISC can provide a 10x to 100x maths performance boost at the same time as 100x code compaction while also securing critical data.
VISC embeds functionality like PUF (Physically Unclonable Function) and TRNG (True Random Number Generation) to secure applications and cryptography.
VISC is described as having a Single-Issue Multi-Execute (SIMEX) architecture,which is reminiscent of the single-issue multiple data (SIMD) DSP-like parallel processing extensions offered in Arm processors.
Differentiated RISC-V
“RISC-V has the potential to be the architecture of choice for ubiquitous edge AI, in the same way that Arm became the architecture for smartphones. To do so, it needs a differentiated, powerful hardware approach that can perform AI calculations much more efficiently,” said James Lewis, CEO of Red Semiconductor, in a statement. He added: “Red is at the forefront with VISC, a RISC-V-based approach that radically streamlines algorithmic processing to deliver faster, smaller, and lower power edge AI solutions. VISC delivers the performance benefits of dedicated hardware accelerators with the versatility of a general-purpose microprocessor. For SoC developers, it enables multiple heterogeneous compute functions to be accomplished with a unified instruction set and hardware core.”
Analyst Jon Peddie, said: “VISC has the potential to reshape heterogenous SoC design for segments like edge AI, much as GPUs have done in the smartphone market, becoming a significant driver of value.”
VISC is delivered as a RISC-V compatible core or IP suitable for use within ASICs or FPGAs, the company said.
VISC’s registers, decoders, and execution engine are optimised for parallel computation of repetitive functions such as fast Fourier transforms, discrete cosine transforms, matrix multiplication and big integer maths. Typical applications that can benefit include AI inference and real-time analytics and video streaming.
In terms of code compaction, a VISC matrix multiply requires only three instructions compared with 100-plus instructions for mainstream ISAs, Red claimed.
Lewis said Red Semiconductor is establishing partnerships with RISC-V, cryptography, and tools companies to support the VISC architecture.
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