# Reduce THD in digitally-controlled PFCs

**Introduction**

Total harmonic distortion (THD) is one of the major criteria in judging the performance of a power factor correction (PFC) controller, and THD requirements have become increasingly stringent. For example, the THD is required to be less than 10 percent at 10 percent load, and in some applications, less than five percent at 20 percent load.

The factors to affect THD are complex (**References** 1 through 6). How to meet the THD requirement becomes a challenging task for a PFC design engineer. This article summarizes the most common yet effective methods to reduce the current distortion in a digitally-controlled PFC. All the methods discussed are analyzed and tested.

**Dynamic loop compensation**

Unlike other power converters, the input voltage of PFC has a very wide range. It can extend from 80 Vac to as high as 265 Vac. Because of this wide input range, PFC electrical characteristics can vary at different input voltages. A good loop-compensation approach at low line voltage may not work well at high line voltages.

It is desirable that loop compensation can be dynamically adjusted, based on the input voltage. For example, some devices (such as TI’s UCD30xx family of digital power controllers) provide dedicated hardware to achieve this goal.

The digital compensator of these types of controllers is a second-order infinite-impulse-response (IIR) filter. The compensator’s coefficients are saved in a set of registers. These register sets are called banks. There are two such banks available and each can store different coefficients.

At any time, only one bank is active and used for the compensation calculation, while the other bank is inactive. The firmware always can load new coefficients to the inactive bank. During the PFC operation, the active coefficient bank can be swapped at any time to allow the compensator to use different control parameters for a different operation condition.

With this flexibility, we can store two different coefficient sets. One is optimized for low line and the other is optimized for high line. The coefficients can be dynamically swapped, based on the input voltage. Therefore, the loop bandwidth, phase margin, and gain margin can be optimized at both low line and high line.

**Oversampling **

Using a current shunt to sense a boost-inductor current is very common in a PFC design. An operational amplifier (op amp) is used to amplify the current signal to a level suitable for a PFC control circuit.

However, this current-signal condition circuit does not provide sufficient attenuation to the input current ripple. The current ripple still appears at the amplifier output. Therefore, if this signal is sampled only once in each switching period, there is no perfect fix location where the signal represents the average current all the time. Hence, with single sample, it is very difficult to achieve good THD.

Digital power controllers like the UCD30xx, for example, can achieve 2×, 4×, 8× oversampling, in addition to the normal single sample per period. An 8× oversampling mechanism is shown in **Figure 1**.

With this oversampling capability, the current signal can be sampled and the converted data loaded to the digital compensator eight times during each switching cycle. It effectively averages the current ripple out, such that the measured-current signal gets closer to the average current value.

Also, the controller becomes less sensitive to noise (signal noise and measurement noise). It has been found that oversampling is one of the most effective ways to reduce current-waveform distortion.

*Figure 1: 8× oversampling.
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*Figure 2. Oversampling test: a) No oversampling, THD=11.14%; *

*b) With 8× oversampling, THD = 5.18%.*

*(Click here and here to enlarge)*

An oversampling test result on a 360W single-phase PFC is shown in **Figure 2**. With all the same operation conditions, the THD is reduced from 11.14 percent to 5.18 percent, just by enabling 8X oversampling.

**Current distortion reduction at DCM mode**

In discontinuous conduction mode (DCM), when the MOSFET is turned off, the boost inductor current starts to decrease. The current will not stop decreasing when it reaches zero. Rather, it will continue going to negative value and an oscillation between the inductor and the total parasitic capacitance at the switching node occurs, as shown in **Figure 3**.

*Figure 3: Current oscillation in DCM.*

*(Ch1: switch node voltage, Ch2: PWM, Ch4: inductor current)*

*(Click here to enlarge)
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The oscillation period and amplitude are dependent on the inductance and capacitance values as well as the operating point. This oscillation results in a significant current distortion and seriously deteriorates the THD (**Reference 2**).

A new control method developed by TI can force the MOSFET to turn on at the point when the first time the oscillating current rising back from negative value to zero, as shown in **Figure 4**. Since the MOSFET always turns on at the same zero-current position, the issue described in Reference 2 is solved, and the current distortion is greatly reduced. Also, because of zero voltage switching (ZVS) and zero current switching (ZCS), the efficiency is also improved.

*Figure 4: A new ZVS/ZCS control algorithm.*

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*Figure 5. ZVS/ZCS control test result:
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*a) No ZVS/ZCS control, THD=10.35%; *

*b) With ZVS/ZCS control, THD=4.76%*

*(Click here and here to enlarge)*

** Figure 5** is a comparison test with and without this new ZVS/ZCS control algorithm on a 360W single-phase PFC. With all the same operation conditions, the THD is reduced from 10.35 percent to 4.76 percent by applying this new control algorithm.

**Adding current reference offset**

As mentioned earlier, in DCM mode the oscillating inductor current can become negative, but the negative current will not show up at the output of the current amplifier. Therefore, the amplifier output does not represent the total inductor current.

This is illustrated in **Figure 6**. The dashed line is the real inductor current, but only the positive part (the solid line) gets measured. Therefore, the measured average current is bigger than the real inductor average current. This inaccurate feedback signal causes input current to be flat at the AC voltage zero-crossing area and deteriorates the THD.

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*Figure 6: Current measurement error due to negative current.*

A simple way to deal with this measurement issue is to add a DC offset on its calculated current reference to compensate the current-measurement error. This can be done by just adding a few lines of code in the firmware.

The above analysis applies to current-shunt-sensing PFC, as well as CT (current transformer)-sensing PFC. **Figure 7** is a test result with this method on a bridgeless PFC with CT current sensing. With the same operating conditions, the THD is reduced from 6.85 percent to 3.03 percent by adding a proper offset on the current reference.

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*Figure 7: a) adding DC offset on current reference test; *

*b) with offset, THD = 3.03 percent.*

*(Click here and here to enlarge)*

**Adding sample-trigger offset **

For a PFC with CT current sensing, since only the inductor rising current (when MOSFET is turned on) is measured, the current needs to be sampled at a specific position. An example would be the middle of the PWM pulse, so that this instantaneous current can be translated into an average current by a specified mathematical equation.

However, due to the gate-driver circuit and power-stage delay, the real inductor current is delayed for a certain time, compared with the related PWM pulse. The actual middle point of the inductor’s rising current is a little bit later than the middle point of the PWM pulse. To compensate for this delay, a sample-trigger offset needs to be added (**Figure 8**).

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*Figure 8: Current-signal delay and sample-trigger offset.*

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*Figure 9: No sample trigger offset, THD = 7.85 percent; *

*b) With sample trigger offset by 512 ns, THD = 5.86 percent. *

*(Click here and here to enlarge)*

** Figure 9** is a test result with this sample trigger offset on a 360W bridgeless PFC test board. The test shows that with all the same operation conditions, the THD is reduced from 7.85 percent to 5.86 percent by adding 512 ns sample trigger offset.

**Using the maximum measure range of ADC**

A digitally-controlled PFC uses an analog-to-digital converter (ADC) to convert an analog signal into a digital signal. Each ADC has its measurement range. The input signal to the ADC should be between zero and its maximum measurement range. Before connecting to the ADCs, high-voltage analog signals such as V_{IN} and V_{OUT}, need to be attenuated to an appropriate magnitude.

On the other hand, its magnitude should not be attenuated to a very small value. This is because the smaller the signal, the larger the resultant signal-to-noise ratio (SNR). Therefore, the voltage attenuator should be designed to give the maximum ADC output at the maximum input.

For example, using an ADC with a measurement range from zero to 2.5V to measure an AC input V_{IN}, and assume the maximum possible V_{IN} is 290 Vac. The maximum peak value of this V_{IN} is 410V. The voltage attenuator (usually just a voltage divider) should be designed to give 2.5V at this maximum V_{IN}, and thus the attenuator’s gain should be 0.0061.

Similarly, in order to get better measurement for a small signal such as the input current measured across a current shunt, the maximum current (including certain percentage of overhead) needs to be amplified to 2.5V so that it has better SNR.

**Using the maximum ADC sample rate**

To regulate the input AC current, the input AC voltage is measured and processed digitally to generate the current reference. Since V_{IN} is a sinusoidal waveform, it should be measured fast enough to generate an accurate current reference with little delay. An ADC sample rate at the range of 50 kHz should be good enough for a 60 Hz AC signal.

Usually, the current-loop reference updating rate equals the ADC sample rate. When V_{IN} is measured, a CPU uses this measured V_{IN} value, along with voltage loop output, to calculate the current reference. Theoretically, the faster the ADC sample rate, the more accurate is the current reference.

However, with the clock-speed limitation, the CPU may not have enough time to calculate the current reference at a very-high ADC sample rate. To fully use the high-speed ability of an ADC, the ADC sample rate can be set higher than the current-loop reference updating rate.

For example, the ADC sampling rate can be set at 100 kHz, while the current loop’s reference is still updated at 50 kHz. A digital IIR filter can be used for these over sampled ADC signals. The benefit of this approach is that the filter can filter out the noise and gives more accurate input-voltage measurement data.

A simple IIR filter example is shown in **Equation 1**,

Y(n) = X(n) + Y(n) – Y(n)/2 **Equation 1**

**Proper maximum duty clamp setting **

At the AC-voltage zero-crossing area, the PFC PWM duty will get close to 100 percent. However, with CT current sensing, its maximum duty cycle should be limited to less than 100 percent. It should leave enough PFC MOSFET off time for CT to reset.

Proper maximum-duty clamp setting is important. If the maximum-duty clamp is too high, the CT may not have enough time to reset and become saturated. Once it is saturated, the sensed-current signal becomes smaller and distorted, which could result in deteriorated THD and even circuit failure.

Conversely, the maximum-duty clamp should not be set very low, either. At the zero-crossing area, the required duty is usually close to 100 percent, and a lower maximum duty means controller cannot provide enough pulse width as required by the control loop; As a result, the current waveform becomes distorted at the zero-crossing area.

**Conclusion**

The factors which affect THD are complex. Multiple contributors to the THD may exist at the same time. There is no single panacea for all the problems.

However, understanding all of these distortion contributors helps a designer to solve the problems one by one and achieve a final goal. This article summarizes the common root causes of PFC current distortion and provides practical solutions to each of them. Test data on a 360W PFC test board validates the solutions and provides a quantitative comparison of THD reduction for the solutions.

**References**

- J. Sun, “On the zero-crossing distortion in single-phase PFC converters,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 685–692, May 2004.
- K. De Gusseme, D. M. Van de Sype, A. P. M. Van den Bossche, and J.A. Melkebeek, “Input-Current Distortion of CCM Boost PFC Converters Operated in DCM,” IEEE Trans. on Ind. Electron., vol. 54, no. 2, pp. 858–865, Apr. 2007.
- P. Todd, UC3854 controlled power factor correction circuit design, Application Note U-134, Unitrode, 2003.
- J. C. Salmon, “Techniques for minimizing the input current distortion of the current-controlled single-phase boost rectifier,” IEEE Trans. Power Electron., vol. 8, pp. 509–520, July 1993.
- Y. K. Lo, S. Y. Ou, and H. J. Chiu, “On evaluating the current distortion of the single-phase switch mode rectifiers with current slope maps,” IEEE Trans. Ind. Electron., vol. 49, pp. 1128–1137, Oct. 2002.
- C. Zhou and M. Jovanovic, “Design trade-offs in continuous current-mode controlled boost power-factor-correction circuits,” Proc. High Frequency Power Conversion, 1992, pp. 209–220.

**About the authors**

** Bosheng Sun** is a Systems Engineer at Texas Instruments where he is responsible for system and firmware design, development and testing for TI’s Fusion Digital Power products. Bosheng received his MSEE from Cleveland State University, Ohio.

** Zhong Ye** is a Systems Engineering Manager for High-Performance Isolated Products at TI. Zhong received the MSEE from Fuzhou University in and a Ph.D. degree in Power Electronics from Toledo University.