Reducing display power to extend mobile battery life
One thing all of us miss when remembering old days of mobile phones is their battery life. As a happy owner of a Nokia 6210, I could afford forgetting a charger for a week of holiday. Of course, the roaming charges back then helped to save battery, but no one will argue the power consumption of today’s mobile devices has grown to become their greatest drawback.
There are many factors that affect the device’s power efficiency, which can be expressed in the number of hours between battery charges. Today, in the era of HD mobile screens there are two major issues that contribute to high battery drain – display brightness and power dissipation in the video and graphics subsystem. In this paper, we will discuss the latter one – smart video and display pipeline in the system-on-chip. Smart, which means providing similar performance to competitive solutions, but requiring much less power.
Challenges for video and graphics subsystems
The modern graphics SoC is required to render high resolutions at high frame rates, and above that perform multiple image post-processing tasks like scaling, rotation, pixel format conversion and others. The typical approach to this challenge is to employ a Graphics Processing Unit (GPU), however, due to its general purpose architecture the power efficiency during specific display processing operations is not optimal.
For such cases, Evatronix developed the PANTA DP IP cores, a family of display processors to take over these display specific tasks from the GPU and thus reduce the power dissipation significantly. The PANTA processors are optimized to execute tasks like multi-layer composition, YUVRGB conversion, rotation, alpha-blending, gamma correction and others before presenting the frame buffer for display. This enables significant reduction of overall SoC dynamic power consumption through partial or complete offload of the GPU. Further reduction of power consumption in the PANTA DP-aided SoC is achieved thanks to preserving the minimum system memory bandwidth through reduction of the number of accesses to the video and graphics frame buffers.
Enhancing existing architectures
Let’s consider an example of a GPU processed display pipeline handling multiple display outputs. The system is displaying graphics frames on two panels with different resolutions – external Full HD (1920 x 1080 pixels) and local HD (1280 x 720 pixels) display. Each frame is composed of three layers. The first is a decoded Full HD video previously recorded by the device’s camera. The frame is stored in the frame buffer in a YUV 4:2:0 format. The other two layers, audio volume control and recording date, are generated in RGB formats by the GPU. A number of operations must be executed before the composed layers can be displayed. These include YUV to RGB video layer conversion, three frames alpha blending, scaling and rotation. In a system presented in Figure 1, the display controllers just transfer the final data prepared by the GPU in the frame buffer.
In this case, energy is wasted by display specific tasks being executed in the GPU, which is optimized to perform different graphics computing operations, in this case 2D graphics rendering. Enhancing existing architectures – Page 2
To improve energy efficiency, PANTA family components might be used. Figure 2 shows an example of a graphics subsystem architecture which utilizes two PANTA DP30 display processors equipped with the PANTA CP20 scaling coprocessors. In this case, the GPU is responsible only for rendering graphics layers pixels and sending them to the frame buffer. The GPU is therefore significantly offloaded because YUV to RGB conversion, alpha-blending, scaling and rotation are handled by the PANTA DP30 and PANTA CP20 units.
In the presented system, the video layer converted by the PANTA DP30 to the RGB format is composed with the other graphics layers and directly displayed on the external panel. At the same time the composed frame is down-scaled from 1080p to 720p by the PANTA CP20 module and returned to the frame buffer. The second PANTA display processor fetches the scaled frame and rotates it by 90 degrees before transmitting it to the local display. Thanks to the PANTA IP scaling and rotation capabilities these additional two operations are not executed in the GPU, and therefore overall power dissipation in the graphics subsystem is significantly decreased. Additionally, since the size of graphics data stored in the frame buffer depends on frame resolution and format, usage of the PANTA components allows reduction of system memory bandwidth up to 40 percent against a typical multi-display solution shown in Figure 1. Total power consumption of PANTA components presented in this use case and implemented in the 40nm LP process is less than 30 mW.
Going further, PANTA display processors enable even higher reduction of power consumption. In some cases all the video and graphics processing tasks can be executed by the PANTA components, thus allowing complete switching off the GPU. Figure 3 presents a use case where the PANTA IP displays decoded video forwarded to the frame buffer by a video decoder. Such a stream requires only rotation and YUV to RGB conversion, and thus eliminates the need to engage the GPU. In this case, the power consumption of the PANTA DP30 component does not exceed 6 mW for the implementation in the 40nm LP process.
Click on image to enlarge
Summary
Because of 3D gaming and HD video playback becoming essential features in mobile devices, it’s crucial that the described video pipeline is power-optimized at the SoC level. Users expect smartphones and tablets to provide decent battery life, also during multimedia activities.
Evatronix PANTA processors improve the power efficiency of the display subsystem without any compromise for the user. It is achieved thanks to the IP performing display specific tasks instead of the GPU and minimizing memory bandwidth of the video/graphics subsystem.
To find out more about the Evatronix PANTA DP display processors, visit Evatronix website at www.evatronix.com/ip
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