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Reference design speeds search in network processing

Reference design speeds search in network processing

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By Graham Prophet



Targeting router and switch applications, the reference design comprises a network search engine evaluation board and a Xilinx field-programmable gate array (FPGA) employing a search SoC control IP to simplify the integration of custom functions. Traditional 400 Gbps network processing systems consist of dedicated SoCs such as ASICs or network processors. By using this reference design, Renesas claims, system manufacturers can quickly deploy 400 Gbps systems with substantially improved performance for routing and switching applications such as video traffic at endpoints.

 

The reference design provides design data on an evaluation board populated with the R8A20686BG, a Renesas NSE SoC capable of up to two billion packet search operations per second, and also includes the newly developed search SoC control IP and control software that would otherwise require a substantial amount of time to develop. Renesas’ NSE SoC reference design combines high-speed packet search with the flexibility of SDNet packet processing technology from Xilinx, ensuring the design will be able to grow with the ever-changing network.

The reference design includes:

– A VCU110 evaluation board populated with a Xilinx Virtex Ultrascale XCVU190-2FLGC2104E FPGA

– A daughterboard populated with the Renesas NSE SoC that is connected directly to the Xilinx VCU110 via FMC connectors

– System-level reference design data integrating the NSE SoC and Xilinx’s SDNet technology

– Search SoC control IP and control software suite

 

The tightly integrated packet processing reference design is optimized for multi-thread requests. By providing up to eight internal search request ports, this solution is able to process multiple requests in parallel, which fully utilizes the available bandwidth and extracts the maximum performance of the NSE SoC. The result is a scalable solution capable of supporting 400 Gbps-class network systems with tables of up to one million entries running at up to two billion searches per second. This simplifies the task of configuring, for example, search operations utilizing multiple Ethernet ports each operating at over 100 Gbps, or multiple search operations using pipeline packet processing, to achieve communication speeds at the 400 Gbps level.

 

The control software, developed in conjunction with the reference design, allows system manufacturers to configure up to 32 independent search tables. System management tasks, including table configuration and maintenance, are done entirely through software with minimum hardware knowledge requirements. Moreover, all management tasks can be performed in real time during live traffic with no interruption, making it possible for reconfiguration post deployment. Applications such as load balancing in a software-defined network (SDN) environment or software-defined infrastructure (SDI) will be able to take advantage of this programmability feature.

 

In addition to this 400 Gbps solution, Renesas offers a 200 Gbps design with the same NSE SoC as well as a low-power 100 Gbps solution utilizing LLDRAM-III memory and an FPGA.

 

Renesas; www.renesas.com/en-eu/products/memory/network-search-engine.html

 

 

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