Renesas adopts AI-driven verification for R-car chips
Renesas Electronics in Vietnam is using one of the latest AI-driven chip verification and debug tools to speed up development of its R-Car automotive designs.
The Japanese company is using the Verisium AI-Driven Verification Platform from Cadence Design Systems to provide root cause analysis of bugs in the chip design, improving the debug productivity.
The platform provides a holistic debug environment from IP to SoC and from single-run to multi-run, enabling fast and comprehensive interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies.
The Verisium platform and apps, including Versium AutoTriage, Verisium SemanticDiff, Verisium WaveMiner, Verisium PinDown, Verisium Debug and Verisium Manager, are integrated with the Cadence Joint Enterprise Data and AI (JedAI) Platform to enable AI-driven root cause analysis of bugs.
“Quality and efficiency are paramount to ensure our R-Car designs are completed on schedule,” said Noriaki Sakamoto, president of Renesas Design Vietnam.
“Cadence’s Verisium Debug allows our engineers to debug from IP- to SoC-level designs. The new waveform format is well-designed for modern verification needs and helps to improve simulation probing performance by 2X. By using the Verisium AI-Driven apps, we could improve the entire debug productivity by up to 6X and our design teams have shortened our overall verification cycle.”
“AI has the potential to reshape the landscape of EDA as we know it,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group of Cadence.
“By bringing together all the inputs and outputs of our verification full flow under the Cadence JedAI Platform, we are able to create a new class of Verisium AI-driven apps that dramatically improves the verification productivity and efficiency for our customers.”
www.cadence.com/go/RenesasVerisium.
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