Renesas boosts microcontroller RTOS support
Segger’s embOS priority-controlled RTOS has been ported to the Renesas V850E2/Mx4 32bit microcontroller series for the development of embedded real-time applications. It is a zero interrupt latency, high-performance RTOS optimised for minimum memory overhead in both RAM and ROM.
This allows embOS/IP, a CPU-independent TCP/IP stack to be used, providing a high-performance library optimised for speed, versatility and memory footprint. The emUSB is a high-speed USB device stack specifically designed for embedded systems, which can be used with embOS or any other supported RTOS.
The V850E2/Mx4 series comprises both single and dual core devices with 2.56 Dhrystone MIPS per MHz per core, 1.4 times higher than the company’s previous V850E2 core. The V850E2 CPU core extends its floating point units (FPUs) to facilitate greater accuracy and range in floating point numbers, making it suitable for applications that require high-speed data processing or complex algorithm calculations. By using the dual core solution, embedded system designers can benefit from the world’s highest processing performance of 1024 DMIPS at a clock speed of 200 megahertz (MHz), while still maintaining low power consumption of 0.88 milliwatts (mW) per Dhrystone MIPS, which is 60 percent less compared to using only one core. In addition, the internal system bus that connects each CPU and DMA controller to the peripheral functions has multiple layers. The bus has a total of three layers: one layer for each CPU, and one layer for the DMA controller. The multilayer internal system bus reduces the overhead due to bus arbitration, achieving high-speed real-time operation.
At the same time IAR Systems has launched version 2.20 of its Embedded Workbench for SH that includes support for thread-safe libraries, allowing safe execution of multiple threads at the same time in an RTOS development. It also includes new debugger functionality as well as integration with Subversion, one of the most popular version control systems on the market. This version provides full support for SH-2A/ SH-2A FPU devices, a popular choice both in the automotive industry and in industrial automation.
The compiler has been improved to optimize for higher execution speed, compared to the previous version. These improvements include options for more aggressive loop unrolling and function inlining. Developers of C++ applications can now also benefit from Virtual Function Elimination (VFE), where unused virtual functions are removed during the build process, resulting in tighter object code.
The IAR C-SPY Debugger is an important part of the integrated development environment for SH. The simulator version of the debugger includes a new Timeline window allowing graphically correlated visualization of the call stack and the interrupt log, both plotted against time. This view provides a clear view of the system’s basic behaviour. Also included is the E10A-USB emulator with new support for software breakpoints, allowing breakpoints to be set during program execution. The profiling tool can now present statistics based on trace data of the application’s performance.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
