Renesas claims record standby power SRAM
This cuts standby power, in which data is still retained, by a factor of 1,000 compared with the normal mode of operation, Renesas claimed. It does this by using dynamic substrate back bias control which is allowed by the SOTB structure.
The ability to significantly reduce standby power while still retaining data in SRAM is expected to extend battery life for IoT, home electronics, and healthcare applications. It may also allow for no battery operation natural energy sources such as light, vibration, or heat.
The technology also provides for dynamic switching, with a low power overhead, between active operation, in which the CPU core performs read and write operations of the embedded SRAM, and the standby mode, in which the stored data is retained.
Conventionally such IoT systems will also use non-volatile memory, either off- or on-chip, to store data when it is necessary to shut down. But for short period intermittent operation it can be better for performance and power saving not to shut down, which can cost thousands of machine cycles to bring the system up.
The SOTB process technology differs builds the active circuitry in a thin layer of silicon above the buried oxide. This allows the creation of dopant-less transistor channel structure, Renesas said. It also allows a reduction in transistor variation which, in turn, allows stable operation at voltages down to around 0.5 V. The ability to control the silicon under the BOX layer allows provision of an on-chip regulator that can dynamically control the embedded SRAM substrate bias.
Next: Three operating modes
Renesas has arranged this to provide three operating modes; normal mode, low-power mode, and high-speed mode. By setting the substrate potential from zero bias to a forward bias, the read access time changes from 4.58ns to 1.84ns, thus achieving a speed increase of 2.5 times faster compared to the normal mode. By applying a reverse bias for standby mode the leakage current is reduced by three orders of magnitude to 13.7nW/Mbit, which is only one-thousandth of the power consumption of the normal mode leakage power.
Renesas has also made a design approach to allow the fine-grained read-pulse optimization and thereby alleviate design margin considerations due to variability.
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