Renesas cuts embedded SRAM standby power in prototype technology
This enables Renesas to quote standby power of 13.7 nW/Mbit and 1.84 nsec high-speed readout. Renesas applied its in-house 65 nm-node silicon on thin buried oxide (BOX or SOTB) process for the prototype development of the embedded SRAM. The prototype SRAM achieves simultaneous high-speed readout during active operation, and ultra-low power consumption in standby mode. The SRAM takes advantage of the SOTB structure by using dynamic substrate back bias control to achieve the lowest standby-mode power consumption, which is only one-thousandth of the power consumption during normal standby mode.
The SRAM would be used in an intermittent mode providing storage at near-non-volatile-memory power levels, but without the power expenditure needed to save to NVM prior to shutdown.
Previous Renesas efforts related to embedded SRAM include prototype of an embedded SRAM with a 28-nm high-K metal gate (HKMG) structure and a high-performance embedded SRAM with a 16-nm Fin field-effect transistor (FinFET) structure, which both adopt state-of-the-art process technologies. These embedded SRAM technologies have been adopted in Renesas’ R-Car automotive infotainment system-on-chips (SoCs). Now, to achieve the low-power performance required for IoT, home electronics, and healthcare applications, Renesas developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.
The SOTB process technology differs from the planar transistor structure formed on the silicon substrate in earlier process technologies as an oxide film (BOX: buried oxide) is buried under a thin silicon layer on the wafer substrate. The technology enables dopant-less channel transistors that do not require doping the thin-film silicon layer. By making the structure a dopant-less channel structure, the variations in the transistor threshold characteristics can be reduced to approximately one-third those of the earlier planar type bulk structure transistors. This reduction in variations has a similar effect to the FinFET structure adopted in state-of-the-art SoCs. Reduction of the variations in transistor performance it achieves stable operation at low voltages around 0.5 V. The adoption of a thin BOX layer in the SOTB process technology also allows significant changes in threshold value characteristics of the transistors by controlling the potential of the silicon substrate under the BOX layer. This is a feature that could not be achieved with the earlier planar bulk structure or the FinFET structure. Taking advantage of this feature, Renesas provides an on-chip regulator that can dynamically control the embedded SRAM substrate bias which enables one of three operating modes (normal mode, low-power mode, and high-speed mode) or standby mode to select from according to the state of the applied substrate bias.
Using this regulator, Renesas confirmed that when high-load computational processing is required, by switching from normal mode to high-speed mode, that is, by setting the substrate potential from zero bias to a forward bias, the read access time changes from 4.58 nsec to 1.84 nsec, thus achieving a speed increase of 2.5 times faster compared to the normal mode. In contrast, in the standby mode, by applying a reverse bias as the substrate potential, the leakage current is reduced by three orders of magnitude to 13.7 nW/Mbit, which is only one-thousandth of the power consumption during standby mode from the normal mode leakage power.
Renesas; www.renesas.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
