Renesas reduces clock power by 30 percent for its new generation of microcontroller chips
The latest MCUs were designed specifically for integrating system control and network processing functions of car infotainment devices on one chip.
In modern MCU designs, clock networks can contribute about a third of overall chip power consumption. Using key technology from the Encounter RTL-to-GDSII flow, Renesas reduced clock power by 30 percent on its new MCUs. Furthermore, the Cadence Encounter Digital Implementation (EDI) System and its new Clock Concurrent Optimization (CCOpt) technology enabled Renesas to automate complex timing closure using clock delay control to and from hard macros simultaneously with datapath optimization. As a result, Renesas engineers were able to successfully deliver an MCU solution that supports multiple high-bandwidth protocols such as Ethernet and MOST (Media Oriented System Transport).
“Automotive OEMs are demanding lower power-consuming devices with smaller footprints and better performance to address broader concerns about the environment and fuel consumption,” said Hiroyuki Suzuki, associate general manager of the MCU Product-design Division of Renesas Electronics Corporation. “The EDI System enabled our engineers to eliminate several manual steps and tape out a 160MHz device with reduced power and area, while hitting our performance target and market window.”
The Cadence Encounter RTL-to-GDSII flow helps design teams optimize power, performance, and area for the world’s most advanced high-performance, low-power MCU designs. The integrated Cadence flow includes Encounter RTL Compiler, EDI System, and signoff-proven Cadence QRC Extraction, and Encounter Timing System. In addition, the CCOpt technology unifies clock tree synthesis with logic/physical optimization resulting in significant power, performance and area improvements.
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