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Renesas samples its first general purpose 32bit RISC-V chip

Renesas samples its first general purpose 32bit RISC-V chip

Technology News |
By Nick Flaherty



Renesas Electronics is sampling its first general purpose 32bit microcontroller based on its own RISC-V instruction set architecture (ISA) core. 

Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market and is aiming at IoT, consumer electronics, healthcare and industrial systems.

The RISC-V CPU core is expected to be used for a new family of microcontrollers to be launched next year alongside the proprietary RX Family and the RA Family based on the ARM Cortex-M architecture. 

Renesas already has a deal with Andes Technology for 64bit RISC-V cores in the RZ/Five general purpose and 32bit cores that it has used in application specific parts, starting with chips for motor control and voice control.

The new 32bit RISC-V core designed by Renesas can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. It achieves performance of 3.27 CoreMark/MHz which Renesas says outperforms similar architectures on the market.

At architectural level the Renesas implementation adds a register bank save function to improve the latency and enable the developer to enjoy its benefits. It is possible to backup and restore the CPU working registers and speed up context switching, in the case of interrupt servicing, or when an embedded RTOS must swap out the currently executed thread in response to an event, to cite two almost immediate examples.

The core also includes several RISC-V instruction extensions to improve performance while reducing code size with compression. The M extension speeds up and optimizes multiplication (and division) operations, using a hardware multiplier and divider unit for fastest instruction execution, while the A extension supports atomic access instructions. This is useful as a foundation for concurrency and exclusive access management typically in RTOS based systems

The C extension defines compressed instructions which are encoded in 16-bits only and particularly interesting because they can easily save memory space for common and frequent instructions allowing the compiler to select those optimizations where possible.

The B extension in the core adds several instructions for bit manipulation, a bit advantage for applications managing peripheral registers, protocols and data structures based on bitfield encoded values where the functionality of a composed set of generic instructions can often be replaced by a single dedicated one.

To enhance the robustness of the application software the core adds a stack monitor register to detect and prevent stack memory overflows. These are quite common but sometimes hard to spot through test coverage alone and can compromise the integrity of the system and generate application misbehaviour at runtime.

The core also includes a dynamic branch prediction unit to make such processing more efficient. The role of the branch predictor is to observe the code behaviour then dynamically infer the next instruction most likely to be executed during such control loops. This can improve the average code execution throughput by making the right guess when choosing the next instruction to fetch for execution.

Besides the standard JTAG debug port, the CPU also supports the two-wire compact JTAG debug interface, which is very suitable for the smallest microcontroller packages where the amount of user application pins can be limited. Several performance monitor registers are also implemented in the CPU, which allows benchmarking the runtime behaviour of the executed code in an easy way.

The deal with Andes has allowed Renesas to build up its development tools to support the new RISC-V chip, which is a key part of the roll out of a family of devices. The tools make use of a compact instruction tracing unit in the chip which provides further insight into the runtime behaviour of the system.

“Renesas takes pride in offering embedded processing solutions for the broadest range of customers and applications,” said Daryl Khoo, Vice President of the IoT Platform Division at Renesas. “This new core extends our leadership in the RISC-V market and uniquely positions us to deliver more solutions that accommodate a diverse range of requirements.”

“We congratulate Renesas on achieving its recent milestone in 32-bit RISC-V MCU architecture development,” said Calista Redmond, CEO at RISC-V International. “This achievement exemplifies how RISC-V ecosystem partners, such as Renesas, are rapidly advancing RISC-V innovation. Our RISC-V community now spans 70 countries with more than 4,000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market.”

Renesas is sampling devices based on the new core to select customers, with plans to launch its first RISC-V-based MCU and associated development tools in Q1 2024. Details of the new MCU will be published at that time.

renesas.com/risc-v.

 

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