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Renesas signs deal with open source ARM competitor

Business news |
By Nick Flaherty

Renesas selected the AndesCore 32-bit CPU cores, based on the open source RISC-V instructin set architecture, to embed into new application-specific standard products that will begin customer sampling in the second half of 2021.

The move is a key step to diversify its processor core technology as Nvidia intends to buy ARM. Alongside the ARM cores used extensively by Renesas  in the RZ, RA and RE families, Renesas also has a CISC core used in the RX family that brought together the microcontroller technologies from Hitachi and Mitsubishi as well as an NEC RISC core for the RH family of automotive controllers.

The move is also a boost to the credibility of Andes for a deal with a major global chip maker. It signed a deal with UK 5G small cell chip developer Picocom back in August for the N25F core taht will be used in a 32 core chip.

“We are thrilled that Renesas, a top-tier global MCU provider has designed Andes RISC-V cores into their pre-programmed application-specific standard products. Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA) for system-on-chips (SoC),” said Frankwell Lin, President of Andes Technology. “Not only does this represent a milestone for Andes, but it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine. Renesas customers will benefit from a modern ISA constructed for the needs of 21st century computing.”

“The scalable range of performance, selectable safety features, and customization options provided by the Andes RISC-V core IP enables Renesas to provide innovative solutions for future application-specific standard products,” said Sailesh Chittipeddi, Executive Vice President, General Manager of Renesas’ IoT and Infrastructure Business Unit. “Customers looking for cost-effective alternative paths for existing or emerging applications will benefit from the reduced time to market and lower development costs.”

The delivery of Renesas’ pre-programmed ASSP devices based on the RISC-V core architecture, combined with specialized user interface tools to set the application programmable parameters, will provide customers with complete and optimized solutions. This capability eliminates the initial RISC-V development and software investment barrier.

The move will also see an extensive network of regional Renesas partners trained with RISC-V development expertise to provide cutting edge and sharply focused customer support that will boost the position of Andes and other RISC-V technology suppliers such sa SiFive.

www.renesas.comwww.andestech.com

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