Renesas specs 90-nm flash at 100million cycles for automotive SoCs

Renesas specs 90-nm flash at 100million cycles for automotive SoCs

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By eeNews Europe

Renesas’ 90-nanometer (nm) one-transistor MONOS (Note 1) (1T-MONOS) flash memory technology can be used in combination with a variety of processes, such as CMOS and bipolar CMOS DMOS (BiCDMOS), and provides high program/erase (P/E) endurance and low rewrite energy consumption. Renesas anticipates that the new flash memory circuit technology will enable it to add flash memory to automotive analogue devices with improved performance and reliability. This circuit technology makes possible the industry’s first P/E endurance of over 100 million cycles under a high junction temperature (Tj) of 175°C, while also delivering low rewrite energy of 0.07 mJ/8 kB (millijoule: one thousandth of a joule) for low energy consumption.

Until now, says Renesas, it has not been possible to add flash memory to the automotive analogue and power devices that control the high-voltage (HV) drivers used for compact motors without changing the base process used to manufacture them. Therefore, storing data for optimising the performance of analogue circuits is typically addressed either by incorporating eFUSE technology or by employing external EEPROM chips. The newly developed flash memory technology limits additional process costs while providing an easy way to add flash memory to automotive analogue and power devices. This means that analogue circuits for connecting sensors and motors can employ devices that mix microcontroller (MCU) logic and flash memory based on the new technology. It has the potential to substantially reduce the number of chips used in motor control systems, while helping to make them more compact, lightweight, and power efficient.

With over 100 million P/E cycles, the memory will be suitable for applications such as automatic calibration or status recording using high-frequency sampling under actual usage conditions in the field. This has the potential to bring greater precision to automotive control and contribute to improved fuel economy.

The memory architecture combines FN tunnelling for P/E operations and high reliability; one-transistor memory cells that allow the mixing of processes with fewer additional mask layers require application of a positive voltage to the memory cell selection gate during read operations. Also, a thinner charge-trapping film is necessary in order to achieve energy-efficient Fowler-Nordheim (FN) tunnelling during P/E operations. Both of these are factors that tend to reduce reliability under the high temperature conditions typical of automotive applications. To address this issue, Renesas has combined the one-transistor flash memory technology with an array architecture technology that eliminates the need to apply a positive voltage during read operations to prevent reduction reliability under high-temperature conditions and assures automotive-level quality.

The high level of program/erase cycles achieved is in part due to tight control of the waveforms used to write and re-write data: technology that weakens electric fields during P/E operations. Adaptable slope pulse control (ASPC) technology enables generation of smoother rewrite pulses as a way to weaken electric fields that can degrade the characteristics of memory cells, boosting P/E endurance to over 100 million cycles.

ASPC is used when applying rewrite pulses, monitoring the current value when pulses are applied and switching automatically to the optimal clock frequency. This lowers current consumption during P/E operations to 98 µA which translates into a rewrite energy of 0.07 mJ/8 KB.

An idling program erase management unit (IPEMU) function enables the flash memory to control rewrites itself when the vehicle’s engine is stopped by a start-stop (anti-idling) system. This makes it possible to terminate the CPU and SRAM that activates the flash control and reduces power consumption during idle state by 99%.

By adopting these technologies, Renesas has developed 128 kB flash memory prototypes. The ability to easily add flash memory to devices employing a variety of processes, combined with low power consumption, is expected to also expand the range of possible IoT applications.


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