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Renesas teams for edge AI compiler

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By Nick Flaherty

Renesas Electronics has teamed up with EdgeCortix to develop a new compiler for its edge AI accelerator.

EdgeCortix in Japan has developed heterogeneous platform-based compiler framework called MERA alongside an AI chip design. MERA was used to develop a new compiler, DRP-AI TVM, for Renesas’ DRP-AI accelerator. The new compiler is available with associated software and tools and works with Renesas’ DRP-AI tools.

The DRP-AI consists of AI-MAC (multiply-accumulate processor) and a reconfigurable processor (DRP). AI processing can be executed at high speed by assigning AI-MAC for operations on the convolution layer and fully connected layer, and DRP for other complex processing such as preprocessing and pooling layer.

The DRP-AI is implemented as a standalone chip, the RZ/V2M, with a 4K-compatible Image Signal Processor (ISP) and Vision-AI ASSP for Real-time Human and Object Recognition, and also in the RZ/V2L alongside a 1.2GHz Dual-Core Arm Cortex-A55 CPU, 3D Graphics, and video codec engine.

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EdgeCortix is a fabless semiconductor design company focused on enabling energy-efficient edge intelligence. It was founded in 2019 with a software first approach, while designing an artificial intelligence specific runtime reconfigurable processor from the ground up for FPGA and custom ASIC implementations.

“We are eager to apply the power of our MERA compiler across many heterogeneous environments, including leading FPGA boards, EdgeCortix’s own custom AI-Inference ASIC and today, integration with Renesas’ DRP-AI,” said Sakyasingha Dasgupta, Founder and CEO of EdgeCortix. 

“We are very pleased that Renesas has realized the value, utility, and performance that our MERA solution offers in developing the compiler for DRP-AI. By applying EdgeCortix’s MERA compiler technology to DRP-AI TVM, this combination will create significant business opportunities and value for both Renesas and their end customers in four key functional areas. Namely, Expanded Model Support, ML Framework Expansion, Support for Floating-point 16 and overall Performance Enhancements.”

The new compiler supports over 20 AI models with 16bit precision, and lower precision support is being developed. It also adds PyTorch support while making the ONNX open interface support more robust. TensorFlow support is to be added in ongoing future work.

A key capability is to support models with operators shared between host CPU and the DRP-AI accelerator in heterogeneous system on chip designs.

“We recognized immediately the value of adding the MERA compiler and associated tool set to the RZ/V MPU series, as we expect many of our customers to implement application software including AI technology,” said Shigeki Kato, Vice President, Enterprise Infrastructure Business Division at Renesas. “As we drive innovation to meet our customer’s needs, we are collaborating with EdgeCortix to rapidly provide our customers with robust, high-performance and flexible AI-inference solutions. The EdgeCortix team has been terrific, and we are excited by the future opportunities and possibilities for this ongoing relationship.”

www.edgecortix.com

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