Japan had wanted to agree a wafer fab initiative similar to that made by TSMC with the US (see TSMC picks Arizona for 5nm wafer fab) but has been rebuffed, according to the report in Taiwan’s United Daily News, which referenced unnamed sources. The UDN report did not indicate how large the investment in the packaging and test facility would be.

Nonetheless an advanced packaging capability would also be of strategic significance. In a geopolitical sense it would beneficial for Japan as, regardless of what happens between China and Taiwan, Japan could have access to leading-edge TSMC wafers made in the US and packaged in Japan.

Japan had been seeking domestic involvement from TSMC in 2020 (see Now Japan wants a domestic TSMC fab) as a response to increasing geopolitical tension around the world, and US moves to draw chip manufacturers on-shore (see TSMC dragged to the altar of US manufacturing).

TSMC has long had a Taiwanese manufacturing policy arguing that it gains economies of scale by focusing on a few locations in Taiwan. However, it has pragmatically relaxed that with fabs in China and the US in recent years. Japan’s METI had signed a preparatory joint venture agreement with TSMC to establish the Japan Advanced Semiconductor Research and Development Center (JASRC), according to the report. Despite Japanese strength in semiconductor manufacturing equipment and materials, TSMC subsequently decided to drop the idea of building a wafer fab in Japan, the report said.

Next: Packaging instead

However, TSMC is making strategic moves to add heterogeneous multi-die packaging to its foundry service offering. Typically packaging and test of ICs has been conducted by a separate set of service providers, also typically based in Taiwan or elsewhere in southeast Asia. These OSAT companies then ship chips on to equipment makers. A clear marker of TSMC’s intentions in packaging was set down In 2020 when TSMC announced plans to spend $10 billion on an IC assembly, packing and test facility in Miaoli, northern Taiwan (see Chiplet-savvy TSMC to build $10 billion assembly and test plant).

The joint-venture with Japan’s government would be TSMC’s way of sharing its expertise in ‘chiplet’  heterogeneous multi-die component manufacturing with Japanese semiconductor companies.

TSMC and Japan are expected to sign a memorandum of cooperation to set up the advanced packaging and testing plant soon.

Related links and articles:

TSMC picks Arizona for 5nm wafer fab

Now Japan wants a domestic TSMC fab

TSMC dragged to the altar of US manufacturing

Chiplet-savvy TSMC to build $10 billion assembly and test plant

Opinion: Money’s not the problem for Europe’s semiconductor rebuild

Lossmaking Indie Semi to go public in $1.4 billion deal

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