RF design in the 21st century
It is striking that logic design methodologies have made huge advances in higher levels of abstraction, tool support, and productivity, while RF design has made comparatively slow progress – until now. I recently discovered a couple of new highly integrated and fully programmable wireless transceivers, and was struck by the similarities between these wireless solutions and FPGAs. Viewed from 30,000 feet, both product types are field programmable, highly flexible, and can be used in a wide range of applications.
The highly integrated wireless products are sometimes classified as field programmable radio frequency (FPRF) devices, which is the term I’ll use from now on. To better understand the impact of FPRF chips, let’s consider how a typical project might run today.
The building blocks of a wireless receiver would be generic with a low noise amplifier (LNA), followed by some filtering. The RF might then be mixed in a tunable superheterodyne (superhet) stage to convert it to an intermediate frequency (IF) followed by a further mixer stage to translate to baseband. Alternatively, direct conversion, also known as zero-IF, is possible using modern semiconductor technology and astute design techniques. The baseband signal would be amplified and filtered, prior to conversion to in-phase and quadrature (I&Q) digital bit streams. The transmit path converts I&Q data streams to analogue signals via DACs, followed by filtering and amplification before being mixed to modulate the RF carrier and on to an RF amplifier.
Conventional design style
A typical “conventional design style” process would use discrete semiconductor components, rather than the new highly integrated chips. The System Architect would define a black box for the RF subsystem detailing all the performance specifications such as frequency of operation, noise figure, dynamic range, output power, and interfaces. The RF Designer will consider architectural options including a superhet scheme using mixers to convert a received signal to a fixed IF, or direct conversion mixer (sometimes called zero-IF), which has seen big advances recently with the latest designs and semiconductor processes. Then the system budgeting begins for every element, where decisions are made about the gain and dynamic range required at each block, including voltages and currents to ensure a proper match and avoid any bottlenecks limiting the overall performance.
For a discrete implementation the designer conducts a scan of products available from a range of semiconductor vendors. The cost, performance specifications, interface levels and timing, availability and lead times, along with power supply requirements would be primary considerations for every function. An evaluation board must be designed, manufactured and populated, to test the transceiver design and identify and rectify any adverse performance. Second order effects like power supply ripple or parasitic oscillation may be difficult to pin down at this stage.
Further complications arise when more than one RF frequency is required, and considerably more complex if multiple bands or different bandwidths are needed. Different frequencies may require tunable components and an agile antenna. Design problems are compounded when the specification calls for complex modulation schemes such as orthogonal frequency division multiplexing (OFDM), wideband code division multiple access (WCDMA), quadrature phase-shift keying (QPSK), or quadrature amplitude modulation (QAM) to be supported. QAM modulation is sensitive to both gain and phase errors, so care must be taken of component matching as well as performance over voltage, temperature, and frequency.
A recently introduced transmission scheme is Multiple-Input Multiple-Output (MIMO), which improves spectral efficiency and gives a diversity gain that enhances the link reliability. It is expected that MIMO will become an important addition to meet the growing demand for data throughput.
After evaluation, the detailed design and integration of the final product begins. The board layout complexity will be defined by the number of semiconductors, discrete components, power supplies, and additional ground planes to separate signal paths. The board needs the creation of a production test and calibration strategy able to identify assembly problems.
New design paradigm
Contrast this with using an FPRF (Figure 1). The transmitter takes digital baseband signals and converts these into modulated RF signals, while the receiver decodes incoming RF and outputs baseband digital streams. The frequency range is programmable over a wide range (0.1 MHz to 3800 MHz from the second generation FPRF, or 100 kHz to 12 GHz with the addition of an Up/Down RF frequency shifter) with RF bandwidths up to 120 MHz. The whole RF chain is specified over voltage and temperature at different frequencies (Figure 2).
Moreover, designers can choose from a number of boards (some including FPGAs) to rapidly start product development. FPRF suppliers provide free printed circuit board layouts (Gerber files) to remove the issue of the tricky RF section and reduce risk and speed up the time to market.
Designers do not need a formal evaluation of the FPRF devices, as they can program the chips on the bench and check out the performance. Potential issues such as component matching, voltage and temperature sensitivities and cross-talk have been resolved during the chip design and qualification, relieving the user of these concerns.
Programming of the FPRF is by loading simple address and parameter details into the device over an SPI connection. This scheme allows the design to be modified in seconds. The revised performance can be tested, enabling the effects of frequency, filter bandwidth and gain to be rapidly explored (see Figures 3 and 4).
Intuitive design tools
The FPRF design tools feature user-friendly and intuitive graphical user interfaces (GUI). The GUI allows full access to all the programmable features, so that different settings can be downloaded in real time. These settings include receive path, transmit path, digital signal processing (DSP) characteristics and I/O configurations. The settings are directly loaded from the PC to provide an instant update to the performance. Once the optimum solution is found, the settings are saved to a file for production programming. The flexibility of the FPRF makes it the ideal component for a software defined radio.
The analogue components on FPRF devices are not the only programmable parts. There can be extensive user programmable DSP blocks dispersed throughout some chips in both receive and transmit paths. For example, in the receiver, the programmable analogue filtering is supplemented by digital filtering to produce a combined enhanced filter function with reduced distortion. The DSP also provides digital frequency synthesis and mixer functions, enabling the IF frequency to be shifted to any desired value within the bandwidth of the on-chip data converters. Therefore, designers can experiment with direct conversion, low and high IF transceiver architectures for their wireless application.
Highly flexible RF design options
The FPRFs have been designed to comply with the requirements for most cellular, commercial and military applications. However, users are not restricted to an “all or nothing” use of the device. On some devices, major blocks can be bypassed or disabled in favour of an external solution (Figure 5). If the on-chip 12-bit ADC provides insufficient resolution, then designers can use an external device. The analogue signals from the baseband gain block are available at pins, and the unused ADCs can be powered-down. There are options to use external filters and to bypass and power-down the on-chip filters. Alternatively, if the system only requires the use of particular elements within the chip, the user can power down the rest of the circuitry. This is similar to the concept of FPGAs where the end user can engage any number of digital building blocks to perform various functions.
The latest devices employ CMOS technology, which has led to enhanced cost-savings and ease-of-use features, to minimize the overall cost of ownership.
The devices require a minimum of external components, resulting in a compact physical solution. They are low power chips, consuming as little as 550 mW, and can operate using a single 1.8V supply rail, reducing the cost of the regulators and the number of board layers needed. These factors all contribute to increased system reliability because there are fewer solder joints and points of failure.
FPRFs can save time and money also during the testing and calibration process. Typically, the production line will involve stages where the RF performance is checked and aligned for optimum performance. The FPRFs offer a fast and efficient solution to this problem with RF loop-back features to test out the basic functionality. Calibration routines can be controlled from either the baseband chip or an on-chip microcontroller, providing a simple and automated capability to tune and align the various blocks to minimize off-sets.
RF designers can benefit from the highly integrated field programmable chips that are now available to bring exciting new products to market quicker than ever before.
Baseband companion chip
In any system there will be a requirement for baseband processing. Several options are available such as dedicated ASSPs, processors, ASIC solutions or FPGAs. All these solutions have merits and disadvantages. ASSP devices are aimed at high volume applications such as small cells (e.g. femtocells). Where the ASSP provides exactly the required functionality, it will typically be priced aggressively.
However, customers wishing to give their equipment additional features to provide product differentiation may require an additional external intelligence, such as a small processor. The baseband function can, of course, be fully implemented in a processor. One advantage is that the processor code will be written by software engineers, with less reliance on hardware specialists. This solution is very flexible, but the extensive processing demands may run into difficulties for high performance systems and result in high power dissipation. ASICs would be expected to offer the lowest unit costs for the devices. Unfortunately, the tooling charges for ASICs have become so expensive for leading edge technology, that it requires a very high volume to justify the expense and longer time-to-market. The final option is to use an FPGA to perform baseband processing and to control the FPRF. Modern devices feature far more than just programmable fabric, as they include significant on-chip memory, dedicated DSP blocks and some also contain ARM processors.
Various tools are available to help designers, either provided by the FPGA vendor or third party suppliers. For example, Altera offers Open Computing Language (OpenCL) conformant software development kit. OpenCL allows software programmers to take OpenCL code and rapidly exploit the massively parallel architecture of an FPGA. It allows kernel code to be emulated, debugged, pinpoint performance bottlenecks, profiled and re-compiled to a hardware implementation. It allows design performance exploration to optimize the hardware/software partitioning.
Paul Dillien is a marketing consultant, having previously worked in the FPGA industry for 15 years, and is the author of “The FPGA Market” report. Paul is a Chartered Engineer and has worked in strategic and tactical marketing roles for leading US and UK semiconductor companies. Contact him via his website: www.high-tech-marketing.co.uk.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
