Rigetti launches 84qubit single chip quantum processor

Rigetti launches 84qubit single chip quantum processor

Technology News |
By Nick Flaherty

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Rigetti has launched its fourth-generation architecture with a single chip 84qubit quantum processor that can scale to larger systems.  

Rigetti’s Ankaa-1 quantum processor uses a new two-qubit gate architecture with tunable couplers to provide higher performance and can easily scale to larger multi-chip devices.

“The QPU is now internally deployed and marks a major leap forward for our technology, customers and the field of superconducting qubits,” said Andrew Bestwick, VP of Quantum Device Architecture at Rigetti. “Relative to past systems, the gates are faster and the connectivity is denser, opening up new possibilities for application and algorithm development. We believe this is the architecture that will bring us to narrow quantum advantage (nQA), and the Ankaa-1 system represents a landmark moment towards achieving that goal.”

The company is working with Riverlane in the UK to use the Ankaa-1 system in its first external partnership.  

The previous Aspen systems used a fixed coupling between neighbouring qubits to control the resonant frequencies. Every other qubit in the lattice is “parked” at a high frequency, so that at rest the frequency separation between neighbours is large and the interaction is weak.

To form a two-qubit gate, the qubit frequencies are modulated closer together to entangle them. This works, but limits how strong the coupling can be and how quickly the qubits can interact, or else the “always-on” interaction at rest will be too strong.

Tunable couplers remove this tradeoff and allow the parking of the qubit frequencies close to each other while turning the interactions off. This just then needs a small change to a tunable coupler to turn on a very strong gate.

This creates a resting lattice without unwanted interactions with the ability to quickly entangle any pair of neighbouring qubits. This has boosted the median two-qubit gate time on the Ankaa-1 quantum processor system to be nearly three times faster than on the Aspen-M-3 system.

Tunable couplers also allow each qubit to have more neighbours. Without the ability to completely turn off qubit-qubit coupling, the Aspen system has to be much more careful to avoid activating unwanted interactions during gates. In practice, this limits the number of qubit neighbours to three and led to the adoption of the octagon lattice. With tunable couplers this limitation no longer applies. The Ankaa-1 system has a simple, densely connected square lattice in which each non-edge qubit can directly interact with four neighbours, enabling more efficient algorithms.

However, these benefits don’t come for free says Bestwick.

“The modest qubit count jump from the Aspen-M-3 system to the Ankaa-1 system, from 80 qubits to 84, belies quite a lot of added supporting infrastructure. For example, each tunable coupler (which actually is itself a transmon qubit, even if we don’t operate it as such) is controlled independently,” he said.

“From this perspective, the Ankaa-1 system technically has nearly three times as many qubits as the previously largest chips in the Aspen product family. The number of control signals routed to the chip has increased from 160 to 317; readout lines have increased from 20 to 28. The dilution refrigerator that encloses the quantum hardware has a new high-density signaling scheme. Meanwhile, the control electronics have been reengineered and control software completely reinvented from the ground up to support the new circuit functionality.”

This requires more sophisticated algorithms, hence the Riverland deal.

“Riverlane is focusing on improving error correction techniques on the new architecture. This early work on the Ankaa-1 system is tightly coupled with Riverlane’s quantum error correction expertise. A key goal of this collaboration is informing future strategies and optimized implementations of error correction,” said Bestwick.

“We are excited to be the first Ankaa-1 system external users,” says Steve Brierley, CEO and Founder of Riverlane. “This project enables us to target real-time error correction decoding with our algorithms on Rigetti’s FPGA hardware, which we hope will help improve performance on future systems.”

As with Aspen-M systems, signals are delivered vertically to the chip from directly above the qubit, without any signal fan-out or routing from the chip perimeter. This means that scaling up to larger chips in the future will be simply a matter of expanding laterally.

The single chip is natively ready for future assembly into a multi-die processor array and Rigetti has demonstrated R&D systems with the 2Q gates operating across chip boundaries with sub-1% error rates.

This will lead to future larger processors by tiling multiple silicon building blocks.

Rigetti now has plans to extend the qubit coherence times through chip design and fabrication changes, reduce the noise from the control electronics, optimize circuit design parameters, and use better signal amplifiers with the Ankaa-2 system anticipated for later this year.;



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