RISC-V ‘100 errors’ reports clarified
Krste Asanović, chairman of the RISC-V Foundation, has published an article at the Foundation’s website pointing out that although a particular RISC-V design failed over 100 tests, with reference to the C11 high-level programming language, a single change to the RISC-V instruction set architecture (ISA) specification could eliminate all these failures
The article stresses that the unmodified Rocket core did not exhibit any illegal behavior because it does not reorder memory accesses aggressively. The problematic behavior occurs when additional re-ordering is done that would be legal under the current version of RISC-V. “It is important to note that a failed litmus test does not correspond one-to-one with errors in the MCM, as a single change in the MCM could remove all litmus test failures,” Asanović said in his blog.
The RISC-V Foundation is the not-for-profit body set up to administer the RISC-V open-source ISA. RISC-V is becoming a standard open architecture for industry implementations with backing from numerous companies including AMD, Google, Hewlett Packard, Huawei, IBM, Micron, Microsemi, Microsoft, Nvidia, NXP, Rambus, Qualcomm, Samsung and Western Digital. The technology, if widely adopted, could be disruptive to the business models of established IP licensors such as ARM and Imagination.
Asanović added that the RISC-V Foundation has been working with the Princeton team since December 2015, as well as with other memory consistency model (MCM) experts, to help tighten up the RISC-V ISA specification to avoid these problems. This work is part of converting the original Berkeley-authored RISC-V specifications into an ISA standard that will be ratified by the RISC-V Foundation. This process is expected to complete in 2017.
The intention is for the MCM changes in the spec to be backwards compatible, such that existing simpler cores would run code written to the new specs correctly.
Asanović went on to say that the Princeton team had also reported on the use of their tools TriCheck and PipeCheck, on proprietary ISAs and shown them to have unresolved bugs in shipping products. “We note that no proprietary ISA vendor has published a formal memory model that they guarantee their products will obey,” said Asanović in his article.
Related articles:
Princeton finds bugs in RISC-V architecture
Linley Group: RISC-V offers simple, modular ISA
Microsemi offers open RISC-V core, in FPGA, for embedded design
Mixed foursome offers RISC-V development support
SiFive launches first RISC-V SoC
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