RISC-V arrives in data centre league

RISC-V arrives in data centre league

Technology News |
By Christoph Hammerschmidt

Ventana unveils highest-performance RISC-V processor to date at 3.6 GHz in 5nm.

Started little more than a decade ago as an open-source experiment, the RISC-V community has continuously expanded both the ecosystem and the technology of the RISC-V processor. California-based Ventana Micro Systems has now catapulted it into the pinnacle of processor technology – the data centre class.

For its now-introduced Veyron family, Ventana aims to make the RISC-V architecture native to the data centre. The Veyron V1 is the first member of the new family and – according to its creators – the most powerful RISC-V processor available today. It will be offered in the form of high-performance chiplets and IP. Ventana Founder and CEO Balaji Baktha made the public announcement during his RISC-V Summit keynote.

The V1 offers single-thread performance competitive with the latest established processors for data centre, automotive, 5G, AI and client applications. The Veyron V1’s efficient microarchitecture also enables the highest single-socket performance among competing architectures. 

The Veyron V1’s performance combined with RISC-V’s open and extensible architecture enables customer innovation and workload optimization. Ventana already sees the V1’s potential as the basis for extending Moore’s Law. This potential, the vendor says, opens the door to further efficiency gains through domain-specific acceleration. This would make it possible to address emerging energy and thermal challenges in data centres.

Chiplet approach slashes time-to-market

The standards-based Veyron V1 compute chiplet and reference platform will enable customers to accelerate time-to-market by up to two years and reduce development costs by up to 75%. Chiplet-based solutions also provide better economics by right-sizing compute power, IO and memory. Composable architectures that leverage chiplets enable companies to focus on their innovation and differentiation to achieve workload optimization. In addition, Ventana offers a Software Development Kit (SDK) that includes a comprehensive set of software building blocks already proven on Ventana’s RISC-V platform.

“Our vision to deliver the most powerful RISC-V CPUs is helping to reshape the next generation of high-performance open hardware architectures,” said Balaji Baktha, founder and CEO of Ventana. “Today, we have a significant first-mover advantage by providing a platform that enables customers to innovate and stand out. Markets that require high compute performance, such as data centre, 5G, AI, automotive and client, will all benefit from our ultra-low latency, open standards-based chiplet solution that enables rapid product development with a significant reduction in development time and cost compared to prevailing IP models. Ventana’s strong roadmap and customer commitment put the company in a prime position for continued market leadership.”

The new RISC-V CPU core is at the heart of the first compute chiplet solution with chiplets supplied by multiple companies. Ventana’s Veyron platform solution also enables the integration of a flexible Domain Specific Accelerator for hardware/software code design. Veyron V1 will be available in the second half of 2023. High-performance features of Veyron V1 include: Enterprise-class RAS, virtualization, robust security, top-down performance tuning, and system IP such as IOMMU and an enhanced interrupt controller. The architecture provides for 16 cores per cluster, high core count multi-cluster scalability up to 128 cores and 48MB of shared L3 cache per cluster. For maximum security, the V1 has been designed with advanced side channel attack mitigations.


Related articles:

AMD pushes CXL, chiplets with latest data centre processor

Codasip, SiliconArts team on RISC-V raytracing graphics IP

Intel muddies the data centre waters with IPU roadmap

Intel joins RISC-V, teams on foundry IP

XMOS announces xCore will be RISC-V compatible


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