RISC-V boost from LLVM 16 compiler
Development with RISC-V chips has seen a significant boost with the latest release of the LLVM open source compiler that underpins many industry tools.
For the first time the architecture has a User Guide for RISC-V Target to document the status of support within LLVM for various RISC-V instruction set extensions. LLVM currently fully supports RV32I, and RV64I. RV32E is supported by the assembly-based tools only while RV128I is not supported.
At the same time, support for the unratified Zbe, Zbf, Zbm, Zbp, Zbr, and Zbt extensions have been removed, while support was added for the experimental Zca, Zcd, Zcf, Zihintntl, Ztso, and Zawrs extensions.
This is also the first version where scalable vectorization was enabled by default, enabling easier development for higher performing systems.
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LLVM updates its compiler technology every six months to keep up with developer requirements.
One of the key issues with RISC-V is the use of custom extensions that can lead to fragmentation of the ecosystem. Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor and roughly parallels the definition of a non-standard extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. LLVM expects to eventually accept both custom extensions and non-conforming extensions and inclusion of a vendor extension will be considered on a case by case basis.
The short forward branch optimisation beneficial to the SiFive Series 7 was implemented and a Syntacore SCR1 CPU model was added.