RISC-V core is optimized for domain-specific applications
The Bk7 was developed for sophisticated modern applications, from security to real-time AI processing, especially for applications using embedded Linux.
The Codasip Bk7 has a 64-bit processor core with a single in-order 7-stage pipeline. The IP is fully compliant with the RV64IMAFDC ISA. The open RISC-V standard allows the core to be configured and extended for individual domain-specific needs.
“General-purpose processor architectures are not a good fit for many application areas and manufacturers are beginning to see that customized, domain-specific architectures beat them in almost every aspect,” notes Karel Masařík, CEO of Codasip. “So, our main aim with Bk7 was to make it the fastest and most customization-friendly design yet.”
The Codasip Studio toolset, used to design the Bk7, makes the design and verification process faster and easier through the automation of necessary tasks. Studio uses a single high-level description of a core written in CodAL, an easy-to-learn C-like language. The description can then be updated with custom changes. Studio uses that to automatically generate a complete customized HDK and SDK, including the full UVM verification environment. Bk7 takes this approach a step further by developing a new, module-based architecture for even easier CodAL editing.
“For Bk7, we enhanced the CodAL language so that it can handle modularized design better, and we based the Bk7 architecture on modules,” explains Zdeněk Přikryl, Codasip CTO. “The modules are basically self-contained building blocks that represent various useful configuration options and can be readily added, removed, or reused across multiple designs. This means that customizing the CodAL description, which is the only non-automated step in Codasip Studio, becomes even simpler and faster. Codasip customers are now able to get a customized core with the best PPA for their domain in a hassle-free way that is truly innovative and unmatched in the industry.”
The off-the-shelf configuration of Bk7 supports the RISC-V atomic and floating-point extensions (both single and double precision), an MMU, and supports the privilege modes required for richer operating systems including Linux. Bk7 also has an internal interrupt controller, dynamic branch prediction (BHT, BTB, RAS), JTAG and RISC-V debug, and standard bus interfaces (AMBA). Integrated customizable options include the branch predictor, instruction and data caches and store buffer. Future releases of Bk7 will feature tightly coupled memories, dual issue microarchitecture, and multicore support.
The Bk7 comes with all supporting tools to deploy the core: the CodAL description (fully editable in Codasip Studio), RTL code of the default configuration, the CodeSpace IDE to write software for the core, C compiler (LLVM and GCC), source files and compilation guide for Linux, and Linux boot demo SoC.
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