RISC-V extension shrinks code size in development tool
Swedish tool developer IAR Systems is supporting a RISC-V extension that reduces the code size in embedded controllers.
The latest version of the IAR Embedded Workbench for RISC-V supports the CoDense extension used in the AndeStar V5 RISC-V processor core from Andes Technology.
CoDense is a patented extension of the RISC-V open Instruction Set Architecture (SA) which helps IAR’s toolchain to generate compact code. This saves flash memory on the target processor while the previously supported AndeStar V5 DSP/SIMD and Performance extensions help boost performance by up to 30%.
Version 3.11 of the IAR Embedded Workbench for RISC-V also supports the “P” extensions (0.9.11 Standard Extension for Packed-SIMD Instructions) and enhanced SMP (Symmetric Multi-Processing) and AMP (Asymmetric Multi-Processing) multicore debugging.
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IAR Systems has already supported the AndesCore RISC-V CPU IP at an early stage, giving engineers a complete development toolchain with a C/C++ Compiler and comprehensive debugger that is also available in an ISO 26262 conforming functional safety certified edition.
CoDense in AndeStar V5 is an Andes-extended feature for code size compression on top of the extensible RISC-V standard instructions and has already been used in the AndeStar V3 processors.
IAR has also added Build and IAR C-SPY Debug extensions for Visual Studio Code, so designers can use the tool within the Visual Studio Code editor.
The C-SPY Debugger gives developers full control of the application in real-time, amongst others by using complex breakpoints, profiling, code coverage, timeline with interrupt, and power logging. Fully integrated code analysis tools ensure compliance with specific standards such as MISRA C (2004 and 2012) as well as the best programming practices like Common Weakness Enumeration (CWE) and CERT C Secure Coding Standard.
Being certified for functional safety development itself, the IAR Embedded Workbench for RISC-V comes with a safety report and safety guide for ten different standards including automotive and industrial applications.
“We are glad that IAR Systems provides full support to AndeStar V5 RISC-V processors, especially including the enhancement of the patented CoDense extension in this release,” said Dr. Charlie Su, President and CTO of Andes Technology. “CoDense increases the code density significantly by double digits and is very welcome in MCU or IoT applications.”
“Thanks to our close cooperation with Andes, we provided early support for the AndeStar V5 DSP/SIMD and Performance extensions and now full support for Andes CoDense, enabling code size compressions on top of RISC-V C-extension,” said Anders Holmberg, CTO at IAR Systems.
“The balance between code size and performance can make a real difference for total return on investment from a product or project. With CoDense support, we give our users the power to tip this balance in their favour.”
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