RISC-V International details recent ratifications
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Ahead of Embedded World next week, RISC-V International has highlighted 40 technical specifications it has ratified in the past two years covering the key areas of efficiency, vector and virtualization.
The specifications primarily address the core areas of efficiency, vector and virtualization for customized and scalable RISC-V implementations across aerospace, AI/ML, automotive, data centre, embedded, HPC, and security.
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“As chair of the Technical Steering Committee and an active participant on several technical working groups, I know first-hand the power of collaboration and its impact on the impressive technical achievements the community have accomplished,” said Greg Favor, chair of the Technical Steering Committee and co-founder and CTO of Ventana Micro Systems.
“Organizations – both public and private – around the world are turning to RISC-V because of its elegance and simplicity. The base ISA is simple and locked. The extensions and new specs ratified are a direct response to membership priorities and industry needs.”
The top RISC-V specification ratified include:
Efficiency: bitmanip, Zc*, Zfa
Virtualization: hypervisor, aia, iommu
Vector: vector, vector crypto, FP16, BF16
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About one-third of the members are in North America, one-third in Europe, and one-third in APAC, with tens of thousands of engineers across more than 4,200 members. The organisation says 13bn cores have been shipped.
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