RISC-V ratifies compressed instruction extensions
RISC-V has ratified its extensions for code compression to reduce the memory requirements when using the open instruction set architecture.
This is particularly important for microcontrollers that have limited memory storage, allowing more complex code to be developed and run by mixing the new 16bit instructions with existing 32bit instructions.
The ratification means that no changes are allowed and any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised. This is ley for industrial microcontrollers that will run the same code the 15 or 20 years.
The Zc and Zcm extensions are part of the RISC-V standard compressed instruction-set extension, named “C”, which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations.
The RVC extension can be added to any of the base ISAs, including the RV32, RV64, and RV128 versions. Typically, 50%–60% of the RISC-V instructions in a program can be replaced with RVC instructions, resulting in a 25%–30% code-size reduction.
- Spanish startup performs RISC-V open core surgery
- CEO Interview: Calista Redmond of RISC-V International at Embedded World
- RISC-V microcontroller cores for easy migration
Zc is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions which only contain 16-bit encoding. The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores. The Zcm extensions all reuse the encodings for c.fld, c.fsd, c.fldsp, c.fsdsp.
wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Related articles
- Top ten RISC-V articles in 2022
- Renesas launches RISC-V voice recognition chip
- Nordic Semi sets up RISC-V design team
- Tackling the challenges of RISC-V
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
