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RISC-V reference design for Intel FPGA module

Technology News |
By Nick Flaherty


Aries Embedded in Germany has developed a RISC-V reference IP design for its Intel-based FPGA module.

The MCXL system on module (SoM) is based on the Intel Cyclone 10 LP family and is the first FPGA SoM to pull out the HyperBus high speed memory technology.

For the MCXL reference IP design, three Quartus projects are available: one for the MCXL-S (SDRAM variant) and two for the MCXL-H (HyperBus variant). All implement a RISC-V core with FreeRTOS, a UART core, and GPIO routed to the PMod connectors and gigabit Ethernet using the Intel TSE MAC.

The mcxl_h_ethernet and mcxl_s_ethernet projects use only 128 KiB on-chip memory to provide RAM for the RISC-V core. The mcxl_h_ethernet_hyperbus project also implements the SLL HyperBus IP Core, available with a time-limited 30 minutes free trial license providing additional 32 MiB of HyperRAM and 128 MiB of HyperFlash.

“The new reference design provides an excellent benefit for all customers to evaluate the MCXL SoM or start their own developments,” said Andreas Widder, Managing Director of Aries Embedded. “The design implements the VexRiscv (open source RISC-V soft-core) running FreeRTOS, as well as Intel Triple Speed Ethernet MAC and the SLL MBMC IP.”

The MCXL SoM is aimed at industrial applications in I/O expansion, interfacing, bridging, sensor fusion, and industrial motor control.

aries-embedded.com; github.com/ARIES-Embedded/mcxl-reference-designs

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