Ceva has launched security IP that protects the communication between separate chiplets used in a heterogeneous system-on-chip design.
The Fortrix SecureD2D, developed by Cevasubsidiary Inrinsix, provides secure authentication and firmware boot/code load between chiplets, which are increasingly used to build complex SoC devices.
The IP consists of a RISC-V controller communicating over a secure bus fabric to hardware-based crypto accelerators which perform rapid encryption and decryption to enable cryptographic functions such as ECDSA, SHA2, AES, and others. SRAM and DMA controllers, a low-level firmware API and a customizable high-level application are also part of the IP package to allow rapid integration into secure chiplets. The IP implements both leader and follower termination points to secure chiplet die that can originate from different vendors and different global supply chains. RIC-V is increasingly popular for security IP with a range of standardised cryptographic insutrction extensions
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Security and assurance are key considerations for the adoption of HSoCs as revenue from systems using chiplets will grow from $3.3 billion in 2020, to $50.5 billion in 2024 says market research firm Gartner. The security of the chiplets is key in the aerospace & defense, industrial and automotive markets in particular, and the Intinsix IP was used in the Department of Defense State-of-the-Art Heterogeneous Integrated Packaging (SHIP) program and has already been adopted by Lockheed Martin and a leading semiconductor company.
“The Fortrix SecureD2D IP enables highly-secure die-to-die communications between chiplets, paving the way for the Department of Defense to streamline the design process and lower the cost of developing chiplet systems. We’re pleased to make this IP available within the DoD SHIP program and we look forward to helping secure the next-generation of HSoC devices,” said Mark Beal, CTO of the Intrinsix Business Unit at Ceva.
Fortrix SecureD2D IP is available for licensing today. Deliveries include RTL, SDC constraints, firmware and documentation; and the IP is suitable for any semiconductor process. Ceva also provides further design services to help integrate and support the security IP and chiplet development in addition to full HSoC design and delivery.
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