RISC-V SoC analysis and debug, from Codasip & UltraSoC

RISC-V SoC analysis and debug, from Codasip & UltraSoC

Market news |
By Graham Prophet

UltrasSoC comments that as RISC-V based SoCs enter the mainstream, there is increasing need for commercial support with production-quality debug, analysis and bring-up tools. This collaboration provides the RISC-V community with capabilities that go beyond those available to proprietary processors and instruction set architectures (ISAs).


While selecting a processor and ISA is one of the first challenges for engineers in architecting a new SoC, the real difficulties come when they try to bring the design to life, to productize and optimize it in the real world. While RISC-V provides an ISA for processor IP, it does not in itself solve all the other problems of support, commercialization or development. This partnership aims to serve that need. Rather than simply adapt legacy solutions to the RISC-V environment, this collaboration delivers a complete solution that will not only accelerate time-to-market, but extend analysis and improvement capabilities beyond initial deployment.


“Our customers demand more than just traditional processor-based debug in order to meet the needs of the IoT era,” said Karel Masarik, CEO, Codasip. “UltraSoC’s broad range of capabilities combined with our commercially proven processor infrastructure, supported on our RISC-V series of Codix-Bk processors, drastically accelerates SoC deployment. We are excited by what this collaboration enables and the benefits it delivers to the new era of RISC-V based SoCs.”


In this collaboration, Codasip provides proven processor IP and infrastructure, while UltraSoC extends this to enable a rich and versatile toolkit for debug, optimization and analytics.


“RISC-V is rapidly becoming an exciting ISA choice for new designs, but suffers from the lack of a proven implementation platform,” said Rupert Baines, CEO, UltraSoC. “Combining UltraSoC IP with proven Codix-Bk IP and debug environment results in a powerful SoC debug, analysis and chip-bring up environment that will dramatically accelerate development time while reducing risk for new SoC starts.”


Both companies declare their commitment to continually evolve their solutions to conform to the RISC-V foundations specifications (








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