RISC-V system-level architecture exploration
The package contains configurable RISC-V core, vendor-specific RISC-V processors, TileLink, DMA, peripherals, RTOS, memory modules and over 20 application templates in IoT, networking, wireless, consumer electronics, automotive and high-performance computing systems. The library components are compatible with the rest of the hardware, software, schedulers and network library from Mirabilis Design. The VisualSim system model provides the first clear view of your product using RISC-V. These models are constructed early in the design phase and far before development has started. This solution enables product designers to evaluate feasibility, eliminate risk and identify system bottlenecks of products using RISC-V. In the VisualSim environment, the user constructs a model of the product, add the traffic and sensor interfaces and defines the user-cases. This model is simulated with different parameter values and scenarios. The generated reports provides visibility into timing deadlines, power consumption, resource efficiency, deadlocks, buffer occupancy, data overflow, quality of service and functional correctness.
RISC-V library from Mirabilis Design contains all the building block required to assemble a product that incorporates a RISC-V, be it a semiconductor component or a supercomputer. The application templates accelerate the modeling effort and enables new modelers to quickly put together a system. The eco-system consists of common trace interfaces, task graph generators, pre-configured reports and a visualizer that pinpoints the exact system behavior. The models can be built as a combination of stochastic and timing-accuracy. All the library blocks combine timing, power and functionality, making it the first RISC-V package that allows for true trade-off studies.
Mirabilis Design – www.mirabilisdesign.com
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