RISC-V trace and debug portfolio simplifies development
As was noted by Gadge Panesar, CTO of UltraSoC Ltd., the trace specification was ratified recently after 18 months of effort (see UltraSoC blog of March 10).
UltraSoC’s trace encoder was donated to the community and is made available via the OpenHW Group. This open-source TE implementation includes test benches and verification tests.
Meanwhile SiFive’s Insight includes many such open-source contributions to develop the growing ecosystem of RISC-V developers, including a C++ cross-platform Nexus 5001 trace decoder for RISC-V. The Nexus 5001 trace specification is an open, well-documented standard that includes an extensive portfolio of processor trace and trace related features.
SiFive Insight is available for all SiFive RISC-V Core IP product lines offered by SiFive Core Designer.
SiFive Insight is supported by many debug and development tool companies including: IAR Systems, Lauterbach and Segger.
“Our mission is to enable higher-quality products with fast time to market, especially in the fast-growing Intelligence of Things and TinyML markets,” said Naveed Sherwani, CEO of SiFive, in a statement. “This will drive the rapid creation of new domain-specific accelerators and embedded devices with on-device decision-making capabilities.”
Related links and articles:
News articles:
UltraSoC secures targeted venture capital for analytic IP
ARM versus RISC-V at European Processor forum
Security IP available for RISC-V
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