RISC-V wireless chip with Adaptive Body Bias reaches pW power

Technology News |
By Nick Flaherty

Researchers in Switzerland and Japan have developed a RISC-V wireless system on chip with anactive power consumption as low as 10µA and an ultra low power standby mode that consumes just 1pW/bit.

The SoC developed by CSEM and United Semiconductor Japan (USJC) operates in near-threshold region at 0.6 V and combines user-configurable power management unit (PMU) and bias generator circuits to implement automatic adaptive body bias (ABB) regulation over process, voltage and temperature (PVT)

“This could mean, for example, keeping the power requirement constant between generations of devices, such as smartphones, which are the same size as the phones we used ten years ago but have 100 times more features. Or using a different kind of power supply, like a tiny solar panel, to run a device,” says Stéphane Emery, head of system-on-chip research at CSEM.

The chip is built in the 55nm C55DDC process from USJC, formerly the Mie Fujitsu Semiconductor (MIFS) joint venture with foundry UMC. This process is tailored for low power and body bias control which uses the transistor’s body potential to dynamically control SoC speed and consumption. A reverse bias is used for low-power cases and forward bias is used for high-speed processsing.

The chip uses icyflex-V RISC-V core with 256 kB RAM and 4 kB ROM alongside the icyTRX Bluetooth transceiver, low voltage ADC/DAC IPs and PMU and Bias Generator that implement the novel automatic ABB.

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Modes are defined by setting the target clock frequency such as a kHz range for Slow mode, MHz range for Fast mode. ABB automatically provides robust operation over PVT for the modes of operation. The different blocks in the SoC can be powered-off using standard power switches and power can also be optimized using ABB.

The 256 kB memory is divided in multiple banks that can be biased independently. When the software requires limited memory, only the minimum size of RAM is active (e.g. configuring Fast or Slow mode) and unused RAM banks are kept in Retention mode. Reverse bias is used for these RAM banks in Retention mode where the banks cannot be accessed but they hold the data and consume as low as 1 pW/bit.

Low-power (for Slow and Retention modes) and high-speed (for Fast mode) versions for both PMU and Bias Generator circuits also coexist on-chip. Users can directly select the versions to use or just select the mode of operation (Fast, Slow or Retention mode) and the suitable versions are automatically activated (the others are powered-off for current consumption reduction). Users can also define a frequency target. The Bias Generator circuit will automatically regulate bias voltages and the clock to ensure functionality over PVT. This Bias Generator circuit is an evolved version from previous works but in this new version a Frequency-Locked Loop circuit (FLL) is used to self-adjust the bias generation and the clock frequency. The FLL also includes an oscillator with configurable length that replicates the critical path of the SoC.

The chip also supports mode switching in real-time, allowing the system to adapt to different application phases and obtain optimum consumption results. The SoC can switch for instance from Fast to Slow mode or from Fast to Retention mode and vice versa at any time in the execution of a software. A mode switching specific circuitry takes care of bias voltage continuity over time to avoid unwanted steps in the bias voltages and gates the clock while bias voltages are varying to avoid clock glitches.

CSEM has developed a demonstrator board where the performance of the SoC is determined by the output of sensors. The SoC is by default in Slow mode at 50 kHz and switches to Fast mode at 8 MHz setting using an external trigger from the Pressure Sensor or the Microphone. Temperature, humidity and current consumption are measured by sensors on-board that are sampled by the on-chip ADC. They are then sent using the icyTRX radio and displayed on a tablet.

Power consumption is 10 µA for the Slow mode and 250 µA for the Fast mode. For long periods of inactivity, the retention mode means the chip consumes 1 µA using an always-on 32 kHz clock.;

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