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RiscFree C/C++ support for Lattice RISC_V soft IP cores

RiscFree C/C++ support for Lattice RISC_V soft IP cores

Business news |
By Nick Flaherty



Ashling has added support for RISC-V soft IP cores from Lattice Semiconductor to its RiscFree development tool.

The RiscFree software development kit (SDK) includes an IDE, compiler and debugger, which now provides software development and debug support for the RISC-V MCU CPU soft IP that run on the Lattice FPGAs .

Since its introduction, Ashling’s RiscFree SDK has been steadily building market share within the embedded tools market and is particularly strong in the RISC-V market where its ease-of-use, broad functionality, plug-in architecture and real-time trace support have made it the go-to-choice for 32-bit and 64-bit RISC core software development.

“We are pleased to announce support for Lattice’s RISC-V MCU CPU soft IP cores and that our RiscFree is now part of Lattice’s tools eco-system for development and debugging. We’re looking forward to enhanced collaboration, particularly between our engineering teams, to ensure that RiscFree is positioned to exploit all additional debugging and analysis capabilities planned for future MCU CPU IP devices” said Hugh O’Keeffe, CEO of Ashling.

The support includes an IDE with full source & project creation, editing, build & debug support, single-shot installer that installs & automatically configures all the component tools to work “out-of-the-box” and automatic source-code formatting, syntax colouring & function folding. The integrated compiler toolchain also includes an integrated QEMU ISA simulator with support for other industry standard instruction & cycle accurate simulators as well as a high-level RISC-V register viewer.

There is also integrated debug support for real time operating systems (RTOS) such as FreeRTOS or Zephyr and project wizards, templates & examples

www.ashling.com/ashling-riscv/; www.latticesemi.com

 

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