RTL Architect cuts design time, scales, improves results, says Synopsys

RTL Architect cuts design time, scales, improves results, says Synopsys

New Products |
By Peter Clarke

It operates at the register transfer level (RTL) and uses a beefed-up data model and prediction engine to allow better results to be delivered in half the time of previous sign-off tools, the company said. Synopsys and ARM are collaborating on RTL Architect to accelerate the development of next-generation cores.

The unified data model delivers higher capacity and scalability allowing the tool to be applied to full-chip hierarchical RTL design flows on contemporary multibillion transistor designs.

In current design practice RTL can be a poor indicator of downstream power-performance-area and this can cause developers to have to go back and rewrite the design to meet the goals of various vertical markets such as artificial intelligence and automotive.

RTL Architect has a prediction engine built-in and enables RTL designers to pinpoint bottlenecks in their source code to improve RTL quality. For existing users of Synopsys PrimePower at the gate-level, PrimePower RTL power estimation is also available, enabling a consistent RTL to signoff power analysis flow.

“Synopsys’ RTL Architect will enable us to quickly explore and validate various architectures at the RTL stage and identify the best one without having to worry about late-stage surprises,” said Hideyuki Okabe director of digital design technology at Renesas Electronics Corp., in a statement issued by Synopsys.

Related links and articles:

News articles:

Synopsys buys Invecas analog IP assets

Analog IP reuse firm gains funds for expansion

Former ARM executives at helm of analog IP startup

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles