RTL compiler ups physically-aware capabilities for complex chip design
Encounter RTL Compiler version 13.1 includes a new suite of physically aware RTL synthesis capabilities that deliver up to 15% improvement in power, performance and area on today’s most complex advanced node chip designs that face timing or congestion challenges. These new capabilities are part of a production-ready physical synthesis engine that enables engineers to use physical aware techniques at the earliest phases of synthesis for better silicon results.
Fujitsu endorses the tool, saying that on a 1GHz, eight-CPU core design it was able to improve timing and area by more than 10%.
As geometries shrink beyond 28nm, changes in interconnect characteristics make it much more difficult to achieve optimal timing and closure. The new RTL Compiler capabilities let design teams address these challenges earlier in the design process so they can achieve faster timing closure, while improving performance, power and area.
The new RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test. Physically aware structuring and mapping can improve performance by more than 10% and area by more than 15% on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesise to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10% by merging single registers into multi-bit registers that share a clock.
"Cadence has re-architected RTL Compiler to weave physical awareness into stages of RTL synthesis that were traditionally logic only, allowing engineers to leverage floorplan and placement data as early as possible in the flow to ensure correlation with the Encounter Digital Implementation System," said Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. Cadence; www.cadence.com/news/RTL
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