The innovative RXv3 core boosts the proven Renesas RX CPU core architecture with up to 5.8 CoreMark/MHz, as measured by EEMBC Benchmarks, to deliver industry-leading performance, power efficiency, and responsiveness. The RXv3 core is backwards compatible with the RXv2 and RXv1 CPU cores in Renesas’ current 32-bit RX MCU families. Binary compatibility using the same CPU core instruction sets ensures that applications written for the previous-generation RXv2 and RXv1 cores carry forward to the RXv3-based MCUs.
The new RXv3 CPU core is primarily a CISC (Complex Instruction Set Computer) architecture that offers significant advantages over the RISC (Reduced Instruction Set Computer) architecture in terms of code density. RXv3 utilizes a pipeline to deliver high instructions per cycle (IPC) performance comparable to RISC. The new RXv3 core builds on the proven RXv2 architecture with an enhanced pipeline, options for register bank save functions and double precision floating-point unit (FPU) capabilities for the highest computing performance, power and code efficiency. The RXv3 core will enable the first new RX600 MCUs to achieve 44.8 CoreMark/mA with an energy-saving cache design that reduces both access time and power consumption during on-chip flash memory reads, such as instruction fetch. Using dedicated instruction and a save register bank with up to 256 banks, designers can minimize the interrupt handling overhead required for embedded systems operating in real-time applications such as motor control. RTOS context switch time is up to 20 percent faster with the register bank save function, claims the manufacturer. Similar to the RXv2 core, the RXv3 core performs DSP/FPU operations and memory accesses simultaneously to substantially boost signal processing capabilities.
Renesas Electronics – www.renesas.com