Samsung 3nm designs can start on Cadence EDA tools
The 3nm design flow and process are described as being suitable for applications in automotive, mobile, data center and artificial intelligence (AI).
The certification means that mutual customers of Cadence and Samsung Foundry have immediate access to circuit design, layout, signoff and verification tools and can begin their 3nm IC designs.
The custom and AMS flow includes the Virtuoso ADE Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design (EAD), Spectre X Simulator, Voltus-Fi Custom Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), LDE Electrical Analyzer (LEA), Innovus Implementation System, and Pegasus Verification System.
“We have validated the Cadence AMS tools along with the entire flow, and it meets our requirements for designing with 3nm GAA process technology,” said Sangyun Kim, vice president responsible for the foundry design technology team at Samsung Electronics, in a statement issued by Cadence. He added that the design flow is available immediately.
Samsung began volume production of 7nm FinFET designs at its ‘V1’ extreme ultraviolet lithography manufacturing line Hwaseong, South Korea, late in 2019 – announced in February 2020. That 7LPP process has a successor, 5LPE, that has been defined for IP re-usability, yield learning leverage, and easy migration from 7LPP.
Samsung has begun making chips using the 5nm process and denied it has had any problems with yield. Samsung Foundry issued a statement in July saying: “Samsung has already started mass production of its 5nm EUV process in Q2 2020 and plans to ramp up volume production in 2H 2020 with an expanded customer base. The yield rates of 5nm process are being improved as planned.” See Could Samsung’s struggles with 5nm yield hit Qualcomm?
In its statement Samsung Foundry added that work on first and second generation 4nm processes is on track.
The 3nm process is set to mark a big change in the process architecture with a move to the use of the nanosheet style of transistor fabrication that can put the gate on all four sides of multiple transistor channels, rather than just three as in the classical FinFET. MBCFET for multi-bridge channel field effect transistor is Samsung’s version of the GAA architecture.
Back in May 2019 Samsung Foundry said production of the 3nm process would arrive in 2020/2021.
Related links and articles:
News articles:
Samsung releases PDK for 3nm gate-all-around processes
Samsung to introduce nanosheet transistors in 3nm node
Samsung wins (some) 5nm business from Qualcomm
Could Samsung’s struggles with 5nm yield hit Qualcomm?
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