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Samsung describes 10nm SRAM

Samsung describes 10nm SRAM

Technology News |
By eeNews Europe



A version of the new 6T SRAM bitcell optimized for size is 38% smaller than a similar part in Samsung’s 14nm process. It measures 0.040mm2 compared to 0.049mm2 for a version optimized for high current.

SRAMs take up as much as 30% of mobile applications processors and smaller size is generally a welcome indication of lower cost per transistor, Samsung noted. However in the case of the 10nm SRAM, small size created a problem.

Samsung's 10nm process shrunk its high density SRAM 38%, and a high current one by a smaller percentage over a prior 14nm device.  (Click here to see a larger image. (Images: Samsung, ISSCC)

Samsung’s 10nm process shrunk its high density SRAM 38%, and a high current one by a smaller percentage over a prior 14nm device. (Click here to see a larger image. (Images: Samsung, ISSCC)

The 10nm SRAM is so small it has unattractive minimum voltage levels due to the effects of process variations. Similar effects have been felt at previous nodes, spawning a variety of compensating SRAM-assist circuits. The ISSCC paper described a new technique that appears to be a small but significant advance on past efforts.  

Overall, the most important thing chip designers need to know is, “the [10nm] fin improves performance, but the back-end resistance does not improve [compared to 14nm], that’s the most challenging aspect of our 10nm finFET process,” said Taejoong Song, lead author of the Samsung SRAM paper in response to a question from a Synopsys engineer.

Back-end resistance will continue to increase through the 7nm node, Song said in a brief interview with EE Times before his presentation. “You expect with a new process everything gets better, but this is not the case,” he said.

Logic could shrink even more than the SRAM cells in the 10nm process given the number of additional techniques the fab can employ, Song told EE Times. Samsung has taped out test chips in its second-generation finFET process but not products yet, he added.

Unlike TSMC which puts finFETs on its 20nm interconnects to create its so-called 16nm process, Samsung’s 14nm process uses the same design rules for its interconnects and finFETs, Song told EE Times. It will continue the practice at 10nm, however he would not give the exact measure of the finest lines used in either process.


Traditionally nodes were named for the finest design rules used. In the latest nodes, chip makers have masked the details of their design rules. Several years ago, one Intel process engineer complained he didn’t understand how the company came up with the name for its 22nm node.

Presumably, most if not all of the 38% shrink of the 10nm SRAM is due to the process itself.  The ISSCC paper described a dual-transient word-line technique to lower minimum voltage levels for the 10nm SRAM to 45 mV for a high current part and 130 mV for a high density version. It did not say what minimum voltage levels would have been without the technique.

Nothing in the paper provided any insights into just what benefits the 10nm process will offer in terms of lower power consumption or higher speeds or whether logic circuits would get the same 38% shrink as SRAM. In his talk, Song only indicated that the 10nm node will offer “similar performance increases” to the 14nm process.

Samsung is on track to start offering mass production of the 10nm finFET process by the end of the year, said Kelvin Low, a marketing executive in Samsung’s foundry group.

The 75.6-millimeter square SRAM is based on a 512 x 16 Kbit macro.

The 75.6-millimeter square SRAM is based on a 512 x 16 Kbit macro.

About the author:
Rick Merritt is Silicon Valley Bureau Chief at EE Times

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