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Samsung extends Cadence deal to 3D chip designs

Business news |
By Nick Flaherty


Samsung’s foundry business has extended its deal with Cadence Design Systems on tools for 3D chip designs.

The two have developed a reference tool flow for the Samsung Advanced Foundry Ecosystem (SAFE) for stacked 3D chips. This flow includes the Cadence Integrity 3D-IC platform for Samsung Foundry’s 3D-IC methodology for the design of hyperscale computing, mobile, automotive and AI chips.

The area of a die can be impacted when chips are stacked in a 3D-IC configuration versus a 2D configuration due to the presence of large 3D structures such as the silicon vias (TSVs) that connect the stacked die.

In addition to blocking standard cell placement area, these structures block routing resources as well. The Cadence Integrity 3D-IC platform alleviates these traditional challenges, letting designers create multiple TSV insertion scenarios and devise an optimal 3D structure placement on a die with reduced wirelength penalties while boosting PPA and productivity.

The platform also lets users perform 3D-IC design planning, implementation and signoff from a single cockpit, making the design process faster and easier.

“Customers creating stacked die designs at advanced nodes are always looking to make use of the benefits of our technologies without compromising PPA,” said SangYun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics.

“The enablement that resulted from our collaboration with Cadence leverages advanced 3D-IC capabilities that provide our mutual customers with innovative techniques to build 3D designs without giving up PPA due to the additional structures introduced with multi-die stacking.

“After working with Cadence successfully on the 3D-IC system planning reference flow, we are confident our customers can achieve their own unique design goals for multi-die stacked designs.”

“Through our latest collaboration with Samsung Foundry, we’re enabling customers to circumvent the typical challenges that arise with 3D-IC design while optimizing PPA in parallel,” said Vivek Mishra, corporate vice president of the Digital and Signoff Group at Cadence.

“The Integrity 3D-IC platform brings together leading silicon and package implementation with system analysis capabilities, helping designers improve overall productivity,” he said. “By leveraging Samsung Foundry’s advanced 3D-IC capabilities and the Integrity 3D-IC platform, our customers have access to an optimal solution for high-quality, multi-die implementation.”

www.cadence.com/go/integrityands

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