Samsung Funds III-V FinFETs in US Lab
The silicon FinFET (3D fin gates on field effect transistors) have become the standard for low leakage and high performance at advanced nodes, but III-V compounds such as indium gallium arsenide (InGaAs) are faster than silicon, prompting researchers at Penn State to combine the best of both worlds.
Penn State’s InGaAs FinFET transistors use a novel five-gate structure grown on an indium phosphide (InP) substrate in its Materials Research Institute’s Nanofabrication Laboratory.
"These FinFETs as of now have been fabricated on InP substrates," Arun Thathachary, a EE doctoral candidate working under professor Suman Datta, told us. "Samsung will own the IP generated from this project." Fellow doctoral candidate Nidhi Agrawal has also contributed to the project.
For years, other semiconductor firms have funded research to fabricate III-V transistors on silicon substrates, including Intel, Sematech, and, more recently, Imec.
The reason everybody is trying to integrate III-V transistor channels with silicon substrates is cost. Not only are InP wafers more expensive, but the entire semiconductor industry is based on equipment optimized for silicon manufacturing.
So even though Penn State is using InP wafers to prove the concept that III-V FinFETs will retain their high mobility at advanced nodes (5 nm) and at lower voltages (0.5 V), Samsung would eventually have to solve the problems of integrating III-V materials with complementary (n- and p-channel) metal-oxide semiconductors (CMOS) on 12-inch (300mm) silicon substrates.
Scanning electron microscope micrograph of a multigate indium gallium arsenide (InGaAs) field effect transistor using an array of five 40nm-wide nanowires. (Source: Penn State)
Thathachary told EE:
- This entire research project is being sponsored by Samsung with the sole purpose of investigating III-V materials for low-power CMOS manufacturing. But as far as integration on 300-millimeter silicon goes, there are significant growth challenges involved in engineering the buffer layers.
Though there have been several publications in this regard over the last couple of years, a high-yield solution for 300-millimeter manufacturing is still lacking. Additionally, III-V materials only provide excellent electron mobility, which means n-channel only. For p-channel devices, there is a significant effort in co-integrating germanium channels alongside III-V to facilitate 300-millimeter CMOS manufacturing. This is also being actively investigated by several companies and consortia, including Imec and Sematech.
So far, Penn State has used three-inch InP substrates on which it deposits InGaAs transistor channels using molecular-beam epitaxy performed at a nearby IQE Inc. facility. On top of the channels, it deposits the five 3D gate fins in what it calls a Multi-fin Hall Bar Structure (MHBS), so named because the researchers claim it is the first structure to allow the measurement of Hall mobility in a multi-fin 3D device.
Thathachary used the MHBS to measure any mobility degradation suffered when going from planar transistors to those with 30nm fins. The researchers found that III-V materials would have a 2-3 times the mobility advantage over silicon under specific conditions.
"InGaAs (intrinsic) is the channel which sits on an undoped InAlAs [indium aluminum arsenide] buffer layer," Thathachary said. "The structures, however, have heavily doped InGaAs as the final layer, as well, to facilitate low contact resistance source/drain regions."
Using IsP substrates mostly solves the lattice mismatch problem that plagues trying to grow III-V compounds on silicon substates. But the researchers’ charter is only to investigate whether III-V FinFETs will work better than silicon at nodes as advanced as 5 nm. To that end, they are experimenting with various formulations.
"Since these structures are grown on InP/InAlAs layers, the channel is lattice matched in the case of the 53% indium composition InGaAs structures," Thathachary said. "We do have a strained 70% indium channel FinFET, as well, where we designed the channel to be thin to prevent it from relaxing."
Thathachary and Datta have spent a year optimizing the processes for the current 3D FinFET, and the success has prompted Samsung to give the lab another year’s funding to prove that it can go to 7nm fins and retain a significant advantage over silicon FinFETs.
The researchers have already found several ways to boost mobility, such as using quantum confinement to force electrons to travel inside the channel, rather than along the surface, which degrades mobility because of the roughness there.
If the researchers can demonstrate a 7nm III-V device that can still beat silicon, Samsung will likely internalize further research to integrate III-V FinFETs n-channels with germanium p-channels on silicon substrates for mass production, probably at the 5nm node.
— R. Colin Johnson, Advanced Technology Editor, EE Times
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
