Samsung packs eight 16Gb DRAM dies into 16GB packages for HPC
Delivering twice the capacity of the previous-generation 8GB HBM2 ‘Aquabolt’, the Flashbolt also sharply increases performance and power efficiency to significantly improve next-generation computing systems. The 16GB capacity is achieved by vertically stacking eight layers of 10nm-class (1y) 16-gigabit (Gb) DRAM dies on top of a buffer chip. This HBM2E package is then interconnected in a precise arrangement of more than 40,000 ‘through silicon via’ (TSV) microbumps, with each 16Gb die containing over 5,600 of these microscopic holes.
The device supports data transfer speeds up to 3.2Gbps by leveraging a proprietary optimized circuit design for signal transmission, while offering a memory bandwidth of 410GB/s per stack. Samsung’s HBM2E can also attain a transfer speed of 4.2Gbps, the maximum tested data rate to date, enabling up to a 538GB/s bandwidth per stack in certain future applications. The company expects to begin volume production during the first half of this year.
Samsung – www.samsung.com
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