Scalable power analysis across 3D chips
Siemens Digital Industries Software has launched its first power integrity tool for analog, digital and mixed signal chip designs.
It’s not often that there are entirely new chip design tools, but Siemens has seen the increasing use of analog and mixed signal chips for the Internet of Things (IoT) and the increasing size and complexity of digital chips as a key area for a power analysis tool.
The mPower tool has been designed to be scalable across analog, digital, and mixed signal ICs, with comprehensive power, electromigration (EM) and voltage drop (IR) analysis for even the largest IC designs.
“We have not previously participated in digital sign off,“ said Joe Davis, Sr. Director, Calibre Interfaces and EM/IR Product Management at Siemens Digital Industries Software. “We started late and could look at the needs and design of a solution [for the whole chip] rather than growing organically.“
“This complements Calibre and PowerPro for power integrity designs. We have designed it from the ground up for analog and digital engines, each engine optimised for the data type they operate on from data loading, extraction, timing, EM and reporting. This is a breakthrough in engineering for the entire system, rather than focussing only on the digital design,“ said Davis. “We do not require large memory machines for the compute and we can scale to thousands of CPUs for full chip dynamic analysis up to billions of transitors.”
He points to the increase in power domains, up to 30 today at 5nm and rising to 55 separate power domains by 2026.
“Previous attempts forced building models like a digital engine – this creates a lot of constraints in the design flow. The analog tools are hierarchcal, but you have to take the waveforms and put them together. We are not hyperfocussed on simulation and can harmonise across analog and digital using Calbre LVS to pull out waveforms at the chip level without having to simulate at the chip level. If there are blocks with strong interactions you do need to simulate these together,“ he said.
mPower operates across traditional 2D designs but also the increasingly popular 2.5/3D chiplet and stacked implementations at any scale, and it easily integrates into existing design flows. Using mPower, IC designers can more quickly and thoroughly verify that designs meet power-related design goals. It works alongside Calibre PERC software, PowerPro software, HyperLynx, and the Analog FastSPICE platforms.
For analog IC designers, mPower replaces rough static analysis and SPICE simulation of select nets with an innovative, dynamic solution that delivers highly accurate, simulation-based EM/IR analysis on the largest blocks and chips. This can speed up overall run times to actually completing first-pass EM/IR analysis of large analog IP blocks, which was previously impossible.
Siemens has worked with a numbe of early adopters, including mixed signal chip designer MaxLinear and multi-core AI chip designer Esperanto.
“mPower allows us to do something we have never been able to do before,” said Dr. Paolo Miliozzi, vice president of SoC Design and Technology at MaxLinear. “And that is to assess EM/IR during tapeout of large analog circuits with confidence.”
The scalable EM/IR engines also analysis for all-digital IC designs. The digital solution integrates into existing design flows to provide power analysis across large designs.
“Before using mPower, we could not do a single-run full chip EM/IR analysis on our 1000+ core 64-bit RISC-V AI chip,” said Darren Jones, vice president of VLSI at Esperanto. “Using mPower enables us to run our 24-billion transistor 7nm AI chip on our server farm with fewer resources, and with better turn-around time than we previously thought possible.”
“Design companies must run both block and full-chip EM/IR analysis to confirm that the power grid delivers the necessary current to the devices, and that wires will not fail prematurely,” said Joe Sawicki, executive vice president for Siemens’ IC EDA Segment. “With our innovative mPower solution, companies now have a fast, scalable dynamic analysis option for analog, digital and mixed signal layouts of any size, as well as silicon-proven accuracy and fast turns for even the largest digital chips.”
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