Scaleable RISC-V module for distributed AI processing

Scaleable RISC-V module for distributed AI processing

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By Nick Flaherty

Antmicro in Sweden has launched a fully open source RISC-V system-on-module (SoM) that fits onto a carrier board to fit up to 18 nodes in a single 1U rack..

The ARVSOM is based around the StarFive 71×0 system on chip developed by SiFive that can run Linux.

The SoM will be compatible with Antmicro’s server-oriented Scalenode platform, released earlier this month, that was originally designed as a baseboard for the Raspberry Pi 4 Compute Module. Used together, Scalenode and ARVSOM will enable building easily scalable and flexible infrastructures consisting of clusters of small RISC-V-based compute units, with as many as 18 Scalenode boards fitting in a 1U rack.

Antmicro has been developing industrial and edge AI systems using vendor-neutral and customizable solutions as well as actively developing and contributing to the RISC-V ecosystem, improving processes as part of RISC-V International and the CHIPS Alliance.

The StarFive 71×0 is also used in the BeagleV StarLight development platform which has just been shipped to beta users, including Antmicro, who will be verifying its robustness and reliability in real life use cases, while the development community focuses on further expanding the RISC-V software support.

The chip uses a dual core U74 CPU from SiFive, two AI accelerators: the open source NVDLA and SiFive’s Neural Network Engine, 1 MIPI DSI and 2 MIPI CSI interfaces, HDMI, Gigabit Ethernet, dual ISP, USB 3.0, while the production version of the SoC to be released later in the year will also have PCI Express.

ARVSOM will also work with other Raspberry Pi CM 4 baseboards.

Antmicro has included software support for ARVSOM and the BeagleV StarLight SBC in its Renode open source simulation framework. This allows system developers to co-develop hardware and software in a virtual environment, with the code behaving exactly the way it would on real hardware. Renode can also be used throughout the development lifecycle to enable continuous testing and integration, as well as prototyping new solutions based on RISC-V, as it features extensive support of the open source ISA.

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