Selecting high-speed ADCs for high-frequency applications
The use of analog to digital converters (ADCs) is becoming well established in frequency domain applications such as radar and direct down conversion receivers. For these high-frequency applications, dynamic range and noise floor are extremely important and provide the drive for the adoption of 12bit converters. The attraction of direct generation of transmission signals and direct conversion of received signals without external down conversion mixers is readily apparent with its advantages in flexibility and reduction in component count. This is particularly true in avionics and space applications where constraints such as component area and power consumption are critical.
As such this holy grail of mixer-less direct conversion has been a preoccupation of systems architects for some time, and now, with advances in semiconductor technology, we can see that components are becoming available to enable this form of system in many more applications. This article covers the converter features required to obtain the best possible performance for high-frequency applications, including flat frequency response, high input bandwidth, low input full scale voltage range and ability to adjust parameters for multiple array systems. It also discusses the system design considerations related to the choice of a high-resolution, high-speed ADC.
Direct down-conversion architecture
The direct down-conversion receiver is becoming more and more relevant in the field of communication systems and radar. Applications such as communications satellite repeaters and synthetic aperture radar earth observation systems would benefit greatly from the use of complete direct conversion transceivers. This technique permits direct digitization of the entire pulsed RF spectrum, bringing more flexibility in the receiver’s performance by enhancing the bandwidth of interest that can be surveyed in one fast Fourier transform (FFT) scan. In this case, a single ADC takes the place of multiple channels of the traditional intermediate frequency (IF) down-conversion.
Applications
L band (1 to 2GHz) benefits from excellent weather penetration, and there are many applications that use it, including communications satellite repeaters, synthetic aperture radar (SAR) earth observation systems, military space surveillance, missile detection and guidance [1], and clear-air troposphere observation.
Remote sensing SAR is an interesting application that uses the relative motion between an antenna and its target region to perform terrain imaging. Here, high resolution and linearity along with the ability to accurately adjust the phase of the sample point are important. Electronic warfare (EW) systems require high sample rate, the ability to scan as wide a bandwidth as possible, and low latency, so that the data will be quickly available.
Multiple array beam-forming applications allow selectivity of direction to improve gain for a particular signal or to reduce the impact of a jamming or interfering signal. In this case phase control features are essential as shown in Figure 1.
Figure 1 Antenna array receiver system Single-Core ADCs
Two key specifications that are important for ADCs that serve in L-band applications are spectral purity and noise floor.
Spectral Purity
A true single-core architecture has significant advantages because it does not rely on internal interleaving to achieve a 1.5GS/s update rate. Hence, no form of calibration is required before or during operation over an extended temperature range. (One feature of interleaved ADCs is their prominent interleaving spurs. The offset mismatch will produce a spur of a fixed frequency; however, gain and phase mismatches will produce spurious frequencies that depend on the input signal frequency. Indeed, calibration is sometimes requested in ADCs using internal interleaving to avoid spurious free dynamic range performance degradation due to misalignment of gain, offset, and sampling aperture delays. )
The single-core advantage can be seen in the spectral purity plot shown in Figure 2. The choice of the frequency is made so that the main signal and its harmonics are close together in the FFT plot. This leaves the rest of the spectrum free to display any other non-signal related spurious signals for example clock spurs. An interleaved ADC may well display spurs in this region but we can see that he signal core shows a spur free zone and a spectral purity of 90dBc.
A single-core architecture also has advantages in terms of latency. Fore examples, latencies as low as 3 clock cycles as found with the EV12AS200 [2] are very useful in applications such as EW and tracking systems.
Fig. 2 Spectral Purity plot for EV12AS200
Noise Factors
The factors behind the signal to noise ratio of a high-bandwidth ADC are given by the equation shown below
nqi is the ideal quantization noise q/√12 and nqd is the deviation from the ideal (DNL). nthermal is the thermal white noise and njitter is the overall jitter contribution. This is made up of internal ADCjitter and external clock jitter.
If the internal clock jitter is around 100fs rms this means that the choice of external clock should give a system with at least that amount of jitter and ideally less for optimal performance. The table below gives examples of noise performance calculation based on the specifications of the EV12AS200 ADC.
Table 1 Typical noise floor calculations
Another important consideration in L-band applications is that performance should remain constant up to the end of the 2nd Nyquist zone. This implies that the bandwidth should cover beyond this area, and the performance parameters such as SFDR, third order inter-modulation figures, and effective number of bits (ENOB) should be flat (see Figure 3).
Fig. 3 ENOB values for EV12AS200
ADC Functions
Given that one important application for this type of ADC is in multi-array designs, the ADC should have the capability to be matched with other ADCs within the array. Hence the gain, offset and phase should have adjustment features. For example, the feature described below would be ideal.
- ADC gain control: fine tuning ( +/- 5%) with 10 Bit DAC ( +/- 0,5 LSB)
- ADC offset control : fine tuning ( +/- 5%) with 10 Bit DAC ( +/- 0,5 LSB)
- ADC sampling delay adjust : 30 ps fine tuning range, 10 Bit DAC : 30 fs step
These features also provide the ability to interleave multiple 12 bit ADCs (to increase actual sampling rate). In addition, a synchronization capability to align multiple channels during the initialization process is essential. This feature could also be shared with a trigger capability that allows the time synchronization of an external digital input with the analog data.
Since the output data rate will be close to the limit of the interface FPGA, an important function will be the ability to de-multiplex (DMUX) this data to reduce the data speed at the expense of introducing more output ports. (A 1:2 DMUX is a solution provided by the EV12AS200.)
Another important feature is the input voltage full scale range. The harmonic performance of the ADC is so low that the system performance could be badly affected by poor spurious levels on the input driver. This problem is reduced if the ADC can accept a low input voltage. The EV12AS200 has an input voltage range of 500mVpp.
Design considerations
The choice of clock source and drive system is critical since jitter is a major contributor to the overall noise calculation. A jitter of around 100fs is ideally required to achieve optimal performance. This implies a source phase noise of 150dBc/Hz or less [3] and additive jitter of any clock buffer well below 100fs.
PCB tracking is also of critical importance, the analog tracking should be matched with the source (or load) to achieve a VSWR of close to 1. The digital tracks should be impedance matched to 100 Ohms and also length matched to better than +/- 2.5mm to ensure that skew differences are not too great for the interface FPGA. The FPGA interface is also a complex part of the system. In order to achieve high data rates, extensive use of the internal serialize / de-serialize (SERDES) units may be needed.
System performance
The performance of the system can be enhanced even further using post processing and real-time techniques, such as integral nonlinearity (INL) correction and using dither to improve SFDR.
The shape of the INL curve plays a large part in the harmonic performance of the ADC. By characterizing this INL and using a look-up table (LUT) in the interface FPGA, the INL can be minimized, which brings benefits for the SFDR performance. The look-up table correction is a simple subtraction or addition of the measured INL value for the code. Using this technique has very little impact on the size of the FPGA and no impact on throughput. In some cases, the addition of a LUT for INL correction can improve SFDR by 10dB.
The SFDR can also be improved by adding an out-of-band noise source to the input data. This can simply be a low-pass-filtered noise generator added to the input signal using a multi-port transformer. This has the effect of moving the input signal around the input scale of the ADC, which reduces the INL effect and improves SFDR (see Figure 4).
Fig. 4 Improving SFDR using Dither
Figure 4 depicts the spectrum showing the harmonics without added jitter. The lower image shows the out-of-band dither and the reduction of the spurious harmonics is clear.
About the Authors
Andrew Glascott-Jones, Applications Engineer for e2v, Mixed Signal ASICs business unit based in Grenoble, France. Andrew has nearly 25 years experience in the design of electronic measuring systems, including: precision metrology, particle sizing, X-ray imaging and laser spectroscopy. e2v’s Mixed Signal ASICs business unit designs and supplies custom ICs predominantly for sensor interface applications in the automotive, industrial and medical markets. Andrew is responsible for the development kits offered by e2v to aid the client during the ASIC development phase. These kits provide I.P. block examples which enable the client to demonstrate proof-of-concept early in the design cycle and effectively pre-develop the full ASIC.
References
1. Dr; Carlo Kopp, “Assessing the Tikhomirov NIIP L-Band Active Electronically Steered Array “, Air Power Australia Analysis 2009-6 , Sept. 2009.
2. M. Wingender et al “12 Bit 1.5 GS/s L-Band ADC on 200 GHz SiGeC Technology”, CIE Radar Conference Oct 2011 Cheng-Du
3. Bar-Giora Goldberg “The effects of clock jitter on data conversion devices” , RFDesign, Aug 2002
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