In their paper “Simultaneous Imaging and Energy Harvesting in CMOS Image Sensor Pixels” published in the IEEE Electron Device Letters, the researchers detail their approach, differentiating their design from other proposed energy-harvesting CMOS image sensors which either have to switch between an imaging and a photovoltaic operation mode or include an additional P-N diode in parallel with the imaging pixel, negatively impacting the pixel’s fill factor.
In the first instance, Energy Harvesting Imager (EHI) must reconfigure the mode of pixel operation by time multiplexing, choosing between lowering the number of image frames per second for more energy harvesting, or prioritizing the imaging operation over energy generation. In the second instance, the additional P-N diode(s) take on valuable pixel real-estate, lowering the pixel’s efficiency.
The authors describe how they modified a conventional EHI architecture by first adopting a hole-based imaging technique, accumulating photo-generated holes in the P+ region as a signal-charge carrier, using two vertically-stacked P-N-P junctions in the standard CMOS process without additional masks.
Although the N-well does not need to be switched for different modes of operation, it can be connected to the same node for continuous energy harvesting (VEH). But the researchers didn’t just flipped the polarities of the wells and implants from a conventional EHI architecture, they further optimized their pixel with three PMOS transistors for reset, selection, and signal readout, while maximizing the fill factor for energy harvesting.
In the optimized pixel structure (Fig. 1c), a P+/N-well (DP1) and N-well/P-sub (DP2) are used for the simultaneous imaging and energy harvesting, similar to the modified pixel of Fig. 1b, but here all PMOS transistors share the same N-well by connecting VEH to the P-sub. By construction, sharing the N-well raises the pixel’s fill factor to about 94%, boosting its energy harvesting efficiency.
To prove their novel pixel architecture, the researchers fabricated a 100×90 pixels CMOS imaging sensor in 0.18 μm standard CMOS process, each pixel measuring 5×5μm2 for a total sensor area of 660×860μm2.
The combination of the pixel’s high fill factor and its large junction area allows for 30μW of harvested power at 120,000 lux illumination. The paper reports that the power consumption of the fabricated CIS core at a 0.6V supply was 3.9μW at 7.5 frames per seconds and 10.08μW for 15fps, respectively, well within the pixel’s energy harvesting budget.
In fact, whole sensor was proven to be self-sustainable under an illumination exceeding 60klux, equivalent to a sunny daylight, while operating continuously at 15fps images. The same device could operate at 7.5 fps under a normal daylight of 20,000 to 30,000 lux. The proof-of-concept device offers the highest power density ever reported, at 998pW/klux/mm2, conclude the authors who have yet to optimize their sensor for low power consumption.
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