Self-timed logic is key to startup’s low-power MCU IP

Self-timed logic is key to startup’s low-power MCU IP

Technology News |
By Rich Pell

Eta Compute, a well-connected startup founded in 2015 and with links to Cadence Design Systems Inc., came out of stealth mode recently claiming it could offer Cortex-M3 cores that consume as little as 2 microwatts (see Startup claims lowest power microcontroller with 0.25V operation). Such low power makes battery-operated sensor nodes with life times of months or even years a possibility, the company claims.

“The basic technology we invented is a kind of logic that is self-timed,” said Paul Washkewicz, vice president of marketing and sales and co-founder of Eta Compute, in an interview with eeNews Europe. He went on to say that it is a form handshaking, self-timed logic but that the key thing was to be able to make it conventionally testable and to deployable on standard CMOS logic manufacturing processes.

Large SRAMs and such things as analog-to-digital converters are operated clocked and Eta Compute has developed interfaces for these.

Essentially Eta Compute has used its connections and knowledge of Cadence timing sign-off software to develop an asynchronous design flow. Circuits can be created in a conventional manner initially before being recompiled using asynchronous gate libraries developed by Eta Compute. This means that Eta Compute’s deep sub-threshold logic can be targeted at multiple manufacturing process nodes – and the company already has libraries for digital processes from TSMC at 55nm, 90nm, 130nm and 180nm.

Circuit development bridges sync-asynch boundary. Source: Eta Compute.

Like any fabless company Eta Compute has been working closely with its foundry but importantly it’s technology required no changes to the manufacturing process and the resultant IP is Eta Compute’s and protectable.

The self-timing approach produces a number of advantages; not least saving the power on distributing a clock signal. But it also means that when operated at full voltage Eta can achieve comparable performance with clocked circuits but the scaling down is immediately available.

Next: Saving how much power?

Washkewicz is reluctant to say how much power-saving licensees can achieve because it is core and peripheral circuit dependent but said Eta customers are not looking for a few percent. “Customers want to see 5x or 4x power savings at the core.

Self-timed logic or asynchronous logic has been attempted before – even with ARM cores –  but performance variability and problems with testing and clocked-to-asynchronous logic interfaces has prevented the technology gaining traction.

Handshake Solutions NV (Eindhoven, The Netherlands) produced the ARM996HS 32-bit RISC processor in about 2006. However, despite a power consumption thought to be about one-third of its clocked equivalent the asynchronous processor failed to gain commercial traction.

Wave Computing Inc. is one company that does make use of self-timed logic, mainly in the pursuit of high performance at conventional voltages. It offers a coarse-grained reconfigurable array for statically scheduled dataflow computing that is based on local self-timed synchronization of circuits.

As clockless logic now claims to offer an advantage achieved deep sub-threshold voltage operation and therefore low power – a Cortex-M3 operating at 0.25V and consuming as a little as 2 microwatts – the technology’s time may now have come. This opens up the possibility of autonomous software-programmable circuits running at 200KHz indoors from solar cells under fluorescent lighting.

Washkewicz explained that a problem with taking clocked logic to the deep sub-threshold voltage regime was that gate-delays become not only long but variable. For clocked logic gate-delay distributions are reasonably Gaussian and tight above 1V but the lower the voltage the more log-natural the distribution becomes with an extremely long tail.

Eta Compute’s advantage is that self-timed logic is insensitive to this gate delay and functionality is preserved. “Everything we can do in self-timed logic we do but there are some things we can’t such as UARTs,” he added.

Next: Test and interfacing

A second significant problem with asynchronous logic was developing test suites that could confirm functionality. “Design for test was one of the things we had to solve. Using formal verification and other methods we’ve solved that problem to our satisfaction and to ARM’s. We’ve added capabilities to mimic scan registers. Level shifters are all built into a wrapper so that from the outside it looks like a synchronous design. It looks like an ARM core, compiles like an ARM core, performs like an ARM core,” Washkewicz said.

Eta Compute has received $3.4 million in a seed-round of funding and Washkewicz pointed out that the company’s approach is generally applicable. ARM cores, being a low-power microcontroller standard, were an obvious place to start but the company has also looked at RISC-V architecture. “There’s no reason why any type of synchronous logic could not be converted to our approach,” he said. He added that Eta Compute likes to be customer-driven. Eta is working with Helion Technology Ltd. (Cambridge, England) on an AES encrypt/decrypt core that will operate at 0.3V to 0.4V.

Washkewicz said he expected the first commercial ICs based on the Eta Compute IP later in 2017. “Our own first silicon came back at the end of 2016 and that allows us to engage with customers.”

Related links and articles:

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Sub-threshold processor startup gets funds
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Sub-threshold design – A revolutionary approach to eliminating power
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