Sematech researchers to probe 15-nm challenges at IEDM
Sematech researchers will report on high mobility channel materials, improved high-k metal gate reliability advancements, advanced non-planar device doping approaches, and resistive RAM (RRAM) memory technologies for scaled CMOS and memory beyond the 15nm node.In one paper they will demonstrate a new, conformal, damage-free monolayer doping technique for 20nm FinFETs which is a promising candidate to address key FinFET scaling issues such as series resistance and short channel control for the 15nm node and beyond.
Another paper will examine a novel physical model of RRAM devices that describes the creation of conductive filaments during forming and electrical transport in high- and low-resistance states. A third paper will identify, for the first time, key factors impacting stress-induced leakage current (SILC) through a comprehensive reliability study of high-k/ metal gate nMOSFETs, including several process changes that promise to mitigate SILC.
The researchers will propose an approach to reducing SILC, thereby improving device lifetime.A fourth paper will analyze BeO films epitaxially grown on Si and GaAs substrates using a conventional atomic layer deposition (ALD) technique. The researchers will discuss the films’ superior physical and electrical properties leading to the feasibility of employing this novel oxide as a gate dielectric and barrier layer in a manufacturing environment.
Sematech will also partake in an evening panel discussion “Is 3-Dimensional Integration at Best a Niche Play?” Sitaram Arkalgud, director of Sematech’s Interconnect division, will join process technology gurus Shekhar Borkar of Intel, SiYoung Choi of Samsung, John Lau of ITRI, and Jan Vardaman of Techsearch, Inc. to explore critical 3-D interconnect issues.
The 57th annual IEDM will be held December 5-7 at the Hilton in Washington, DC. Meanwhile, next week at the ISMI Manufacturing Week, a symposium on semiconductor manufacturing issues, Victor Vartanian, Films Metrology Project Manager at International Sematech Manufacturing Initiative (Albany, NY) will present what Sematech sees as metrology challenges for next-generation 3-D transistor and memory structures.