SemiDynamics teams for multicore RISC-V chiplet boost
Semidynamics in Spain has teamed up with SignatureIP in the US to combine multi-core RISC-V IP with CHI interconnect for the development of the latest chiplet AI chips.
SignatureIP’s Coherent network on chip (NoC) IP is designed for chiplet designs and supports a transport layer for chiplet communication using ARM’s Coherent Hub Interface (CHI) interconnect standard.
SemiDynamics has developed a series of RISC-V multi-core sub-systems, including a vector unit, that can be easily configured for high performance and low power.
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The C-NoC IP is a directory-based architecture with distributed home-node support and optional system level caches for high performance. SignatureIP’s inoculator.ai tool automates the generation of a physically-aware NoC for a system. Combined with the automation tool and a simple licensing model, the process of evaluation, licensing, and implementation becomes an easy task for SignatureIP’s customers.
The SignatureIP network on chip IP for chiplet designs
“Working closely together with other members of the RISC-V community is one of the driving forces of RISC-V’s rapidly growing success. There is a natural synergy between the two companies that has resulted in a solution that enables cutting edge, multi-cores chips to be created,” said Roger Espasa, CEO and founder of Semidynamics.
“SignatureIP’s C-NoC CHI interconnect solution makes it very straightforward to lay out the Network on Chip (NoC) for multiple cores on a chip using our mature, proven technologies which minimizes risks and accelerates time to market.”
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Kishore Mishra, SignatureIP’s CTO, added, “Semidynamics revolutionized the 64-bit RISC-V processor with cores that are fully customizable using its ‘Open Core Surgery’ approach. This goes deep into the core and is not the tweakable approach typically found in IPs. Combining our technologies now enables multi-core chip designs to be created on this fully coherent RISC-V/CHI platform and then prototyping on an FPGA to demonstrate the integrated performance. We have fully tested them together to ensure compatibility and minimization of verification time.”
www.semidynamics.com; www.signatureip.ai
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