Semidynamics is working with interconnect IP supplier Arteris on next generation RISC-V system on chip designs.
The two are aiming to have a demonstrator platform in early 2024 using the Atrevido and Avispado 64-bit RISC-V processor IP cores and the Arteris Ncore cache coherent network-on-chip (NoC) system IP.
The combined solution delivers interoperability to speed up the development of AI/ML and HPC designs.
- SemiDynamics teams for multicore RISC-V chiplet boost
- First fully coherent RISC-V Tensor unit for AI chip design
“For markets like machine learning, key-value stores and recommendation systems, we optimize our customizable RISC-V processors and supporting technologies, such as Vector Units, Tensors Units and Gazzillion™, to deal with the computing of highly sparse data, with long memory latencies, and high-bandwidth memory systems,” said Roger Espasa, CEO of Semidynamics. “Efficient data transport within our cores and between chips and chiplets is vital for overall system performance. Partnering to pre-integrate with Arteris’ Ncore cache coherent technology will result in accelerated project schedules for our mutual customers.”
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“Our goal is to support our customers’ choices on processor IP while providing the SoC connectivity backbone for the emerging RISC-V ecosystem and its use in combination with other processor architectures,” said Michal Siwinski, CMO at Arteris. “Our collaboration with Semidynamics supports our mission to catalyze SoC innovation so our shared customers can focus on dreaming up what comes next and creating leading-edge products, including those supporting the rapid evolution of AI.”
The demonstrator design integrates a Semidynamics’ four-core RISC-V cluster using the Ncore cache coherent NoC technology by Q1 2024.