Seminar; Addressing SoC power challenges; UK, May 13th 2015
Low power SoC design, says Synopsys, is a system design challenge which does not stop at the border between hardware and software. Enabling a system to perform with low power efficiency requires the right SoC architecture and perfectly matching power management software.
This seminar introduces ways for the SoC architect and the software developer to address their SoC power challenges early in the development cycle with virtual prototyping. Nick Gatherer, Modelling Engineering Manager, ARM opens the seminar with a keynote speech followed by two forty-five minutes sessions which will provide technical overviews of the specific use-cases and solutions available today from Synopsys and ARM.
Session one will introduce how virtual prototypes enable early quantitative analysis of power and performance trade-offs to determine the right SoC architecture with Synopsys Platform Architect, including:
How to partition the SoC application into fixed hardware accelerators and software executing on a processors, determining the optimal number and type of each CPU, GPU, DSP and accelerator
How to partition SoC components into a set of power domains to adjust voltage and frequency at runtime in order to save power when components are not needed
How to confirm the expected performance/power curve for the optimal architecture
Session two will introduce how virtual prototypes enable the early bring-up and test of power management software and power-aware software development.
The Seminar is aimed at System Designers, SoC Architects, Software Developers, and Project Managers; further details and registration are at; https://www.synopsys.com/Company/Pages/soc-power-vp.aspx
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