The flat field transistor, an idea first disclosed by Semiwise (Glasgow, Scotland) in 2018, offers a solution to DRAM scaling problems, the company said.
It does this by improving the margins for DRAM sense amplifiers built using such transistors.
Semiwise observed that while the DRAM cell transistor has gone through many changes – from recess gate to saddle FinFET – the transistors in the sense amplifiers and peripheral circuits continue to be manufactured using bulk MOSFETs.
However, the statistical variability (mismatch) of the bulk MOSFETs eroding the sense amplifier margins. Manufacturers have added offset compensation circuits or in the case of SK Hynix introduced recess gate (RG) transistors into sense amplification but incurred increased manufacturing complexity, cost, and reduced performance.
Semiwise claims that the FFT can deliver a 50 percent reduction in statistical variability compared to bulk MOSFETs of identical dimensions.
This is complemented by 30 percent performance increase and 5 percent reduction of the manufacturing costs compared to the equivalent bulk CMOS technology transistors.
In a statement Professor Asen Asenov, CEO of Semiwise, said: “In the last 20 years I have been focusing my attention to the modeling and simulation of statistical variability in contemporary and future CMOS technologies. Simulation tools developed in my research group and former company, Gold Standard Simulations, are now in the heart of the Synopsys variability aware Design Technology Co-Optimisation (DTCO) flow. I am delighted that the use of these technology and tools has enabled Semiwise to develop the FFT technology that can revolutionizes the DRAM scaling.”
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