Semtech-Snowbush IP supports CEI 25G and 28G on 28-nm PHY IP platform

Semtech-Snowbush IP supports CEI 25G and 28G on 28-nm PHY IP platform

Technology News |
By eeNews Europe

The SBMULTC2T28HPM28G SiIP PHY is targeted for the new generation of chips supporting emerging Exascale computing, Terabit networking, and Petabyte storage markets. Each of these markets requires a PHY developed in a CMOS-based process to support the large digital gate counts necessary in today’s SOCs. The PHY is capable of being deployed in a multi-lane macro to support the highest I/O bandwidth possible with the lowest power per bit transferred.

“We are working with Semtech-Snowbush IP, using our extensive high speed experience, to provide a high-quality solution with fully characterized operation of the 28G PHY platform on the TSMC 28nm HPM process node,” said Naveed Sherwani, CEO of ASIC design firm Open Silicon. “This ultra-low power and high-performance SerDes combined with our implementation experience will allow us to enable our ASIC customers to bring unique and differentiated solutions to market.”

“Semtech-Snowbush IP has developed mixed-signal IP for more than ten years and our IP is in products shipping in millions of units per year,” said Roger Levinson, Vice President and General Manager of the Strategy and Systems Innovation Group at Semtech. “This new generation of IP targets the chip-to-chip and chip-to-module SOC/ASIC networking market requiring 25Gbps speeds to maximize I/O bandwidth. We are leveraging our years of experience developing platform-based SerDes/PHYs to provide performance and flexibility, while continuing to focus on efficient delivery and superb customer support.”

The SBMULTC2T28HPM28G SiIP PHY can be programmed to support multiple standards each with specific electrical performance characteristics. The area, power and latency have been optimized to minimize the impact when used in an SOC, ASIC or ASSP.  A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments.

The new platform represents the eighth generation of a programmable analog front end that Semtech-Snowbush IP pioneered for handling many standards from a single silicon macro. The architecture was initially developed at 65 nm and was ported to 40 nm. At 28 nm, the architecture has seen three generations of silicon and is shipping in production.

The SBMULTC2T28HPM28G has an analog front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing.  The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis and pre-emphasis.

The Rx path is also highly programmable to meet the requirements of many serial I/O applications. Advanced equalization compensation reacts to the actual channel characteristics and extracts clean data that is provided to the on-chip parallel interface. Firmware supports the calibration and adaptation in both the Rx and Tx data paths. Implemented through a digital control interface, the software provides a flexible means of adjusting performance to meet different channel characteristics.

The Rx architecture includes a multi-stage continuous time linear equalizer (CTLE), passive linear equalizer (PLE) and variable gain amplifier (VGA). The receive path also includes a decision feedback equalizer (DFE) for crosstalk suppression and extended reach. All stages feature digital offset calibration and adaptive equalization to handle a range of channel conditions. The Rx architecture supports both AC and DC coupling.

The RX also includes a high bandwidth data clocked CDR to achieve high jitter tolerance. The CDR relies on a digital architecture and includes a sampling phase adjustment capability.

The receiver includes a non-destructive on-chip eye monitor to allow the user to “see” the eye opening at the receive slicer after the application of both transmitter and receiver equalization. This capability can be used to help adjust the transmitter and receiver equalizers and characterize link margin.

The TX architecture includes a source series terminated (SST) transmit driver with a feed forward equalizer (FFE).  The FFE has per-cursor and post-cursor taps with both manual and adaptive control.

The TX clock generation is based on a fractional-N LC-PLL for superior jitter performance. An advanced, digitally assisted calibration approach is supported by firmware (same as Rx). Digitally controlled calibrations include TX termination, TX PLL frequency, TX PLL amplitude, TX phase alignment and DCD. Optional digital control supports link training.

The SBMULTC2T28HPM28G includes a minimal latency on-chip digital interface. Multiple parallel interface widths are supported and the digital interface is designed to inter-operate with industry available PCS and MAC (link) layer logic.

Availability and Pricing

The Silicon IP PHY will ship in October 2013 (as GDS). System-level models are available now under NDA for performance testing and integration.

More information is available on

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