Serial interfaces for high speed ADCs
In medical applications such as magnetic resonance imaging (MRI), ultrasound, CT scanners, and digital X-ray, high channel count analog-to-digital converters (ADCs) are used to sample large arrays of data. Serial interfaces are used to acquire the sampled data to reduce the number of pins on the ADC and FPGA. In addition, routing of a high speed serial interface saves board space. With board real estate at a premium and FPGA pins a valuable commodity, the advantages of serial data converter interfaces over parallel are clear.
Today, there are two choices of serial interfaces that are suitable for high speed data converters. The first is a serial clock-data-frame (CDF) interface, which combines a serialized LVDS (low voltage differential signaling) data stream, as well as a differential clock to accurately collect this data and a framing clock to establish data sample boundaries. The second choice uses the JESD204 standard, where the clock is embedded into a high speed gigabit-per-second (Gbps) two-wire serial data stream.
Both interfaces have their own advantages and disadvantages. Because of the higher power requirement of the current mode logic (CML) pairs used to drive the high speed JESD204 interface, serial LVDS is preferred for lower power, high channel count and portable designs. But it takes over where serial LVDS leaves off.
Benefits of Serial LVDS
Serial LVDS output format reduces the number of digital I/O required between the ADC and FPGA, saving FPGA pins, board space and cost. In addition, by implementing a serial interface on the data converter, the number of pins required is greatly reduced, thus enabling much smaller package sizes. This benefit is greatly realized on high channel count designs.
The choice of whether to use a serial LVDS interface over a parallel interface will depend on whether the application can tolerate the increase in power consumption, and whether the FPGA has the power to process the high speed data stream.
The LTC2195, 16-bit 125 Msps dual ADC with serial LVDS outputs has a power dissipation of only 216mW per channel. However, the serial LVDS interface adds 31mW per channel over using the dual parallel output version LTC2185 (see Figure 1 for complete family chart). This family of 16-bit high speed ADCs offers excellent SNR performance of 76.8 dB at baseband, as well as 90dB SFDR while offering very low power dissipation from a 1.8 V supply.
Figure 1: Linear Technology’s 16-bit low power, high speed ADC family
For high speed ADCs, aligning the data clock, the frame clock and the data usually requires a phase-locked loop (PLL) in both the transmitter and receiver to align the data clock properly. This alignment becomes very difficult at gigahertz speed and the speed of the data transfer is limited mainly by the receivers. Ultimately, this 6-wire method of serial transmission is not generally done above 1GHz, limiting either the speed of an ADC or its resolution.
For a 16-bit high speed ADC, this limits the sampling frequency to 62.5 Msps. To achieve higher sampling frequencies, two or four lanes per ADC channel can be used. Using two lanes, the serial data rate is halved, with even and odd bits split between two serial data stream differential pairs. Using a two lane mode, a 16-bit 125 Msps ADC will have a serial output data rate of 1Gbps. The LTC2195 serial LVDS family has an additional four lane mode which allows for a much slower data transfer rate of 500 Mbps using four differential pairs per channel, for a total of 20 lines including the differential frame and clock pairs (see Figure 2).
Figure 2: Digital output configurations for the 16-bit low power ADC family
This enables interfacing to cheaper, lower speed FPGAs. To put the number of required digital output lines in perspective, using parallel LVDS outputs would require 32 lines per channel.
Today ADCs are available with double data rate (DDR) LVDS outputs which require only 16 lines per channel. Using this option, the data rate at the output will be twice the sampling frequency. Dual 16-bit ADCs like the LTC2185 also offer a choice of DDR CMOS outputs, which reduces the number of data lines required to just 8 lines per channel.
When you consider a single high speed ADC like the 16-bit 125 Msps LTC2165, it no longer makes sense to provide a serial LVDS interface, since there is no difference in the number of data lines required. DDR CMOS uses eight parallel output lines versus two lane serial LVDS (required due to the sample rate being greater than 62.5 Msps) which also uses eight lines (four lines for data and four lines of data and frame). In addition, serial LVDS raises the power consumption of the device, which is a concern in portable applications.
For high channel density medical applications, Linear Technology now offers the octal 14-bit 125 Msps ADC, LTM9011-14, a new low power device which offers signal to noise ratio (SNR) performance of 73.1 dB and channel isolation of better than -90 dBc in a compact 140-pin 11.25 mm x 9 mm BGA package.
For optimum performance, in addition to the space savings, the device integrates all necessary bypass capacitance close to the die. At 125 Msps the power dissipation is only 140 mW per channel. The 80 Msps (LTM9009-14) and 105 Msps (LTM9010-14) versions consume 94 mW per channel and 113mW per channel, respectively with lower sample rate, lower power versions in development. For portable applications, the LTM9011 family includes a sleep mode that reduces power dissipation to just 2 mW. The LTM9011 offers a serial LVDS format, and a two lane output mode for sample rates above 62.5 Msps.
Digital designers may be all too familiar with the challenges of routing high speed digital lines between ADCs and logic devices. Great care must be taken to ensure sufficient spacing between the high speed traces as well as ensuring the digital signals do not cross analog boundaries. Poor layout results in the digital switching noise feeding back into the ADC’s analog inputs to degrade the overall system performance. The LTM9011 family provides a flow-through pinout, reducing the required board area for routing data I/O lines and simplifying layout to minimize issues with digital feedback (Figure 3). Additional options include a data output randomizer that reduces digital feedback, seven programmable LVDS output current levels, internal 100 ohm LVDS output termination resistors, and digital output test patterns. These settings can be easily programmed via SPI or hard-wired for a reduced set of operating modes.
Figure 3: 14-bit 80-125 Msps octal ADCs offer flow-through pin-out
for easy routing to FPGA
All of these serial LVDS ADCs from Linear Technology are available for evaluation using demo boards fitted with the VITA-57 FPGA Mezzanine Connector (FMC). Using the powerful PScopeTM QuikEvalTM II software, engineers can evaluate the performance of multiple input channels in parallel. PScope software is Linear Technology’s high speed ADC evaluation software. For a simple program it does complicated calculations in seconds.
PScope software allows engineers to evaluate the signal to noise ratio (SNR), spurious free dynamic range (SFDR), total harmonic distortion (THD), as well as other key parameters of high speed ADCs quickly and easily. The PScope tool can also perform more complicated calculations such as intermodulation distorting from a two tone test, or adjacent channel power ratios (ACPR) from a spread spectrum signal with the click of a button. It also supports multiple channel ADCs like the LTM9011, allowing the measurement of eight ADC channels simultaneously.
Figure 4 shows a screen shot of the powerful features of the PScope data collection and analysis software tool.
JESD204 High Speed Serial interface
8B/10B encoding, originally invented in the 1980s by IBM, eliminates the need for a frame clock and a data clock, which make single transmission line pair communications possible at serial data rates above 2GHz. The unique features of 8B/10B encoding allow the data clock to be embedded in the data itself, and the framing to be maintained with COMMA characters through initial frame synchronization.
The JEDEC specification JESD204 defines the protocol and electrical characteristics required to standardize the implementation of this coded interface for data converters, which has enabled a new generation of faster, more accurate serial ADCs, such as Linear Technology’s LTC2274, 16-bit, 105 Msps ADC with 77.6 dB SNR and 100 dB SFDR. The JESD204 interface takes advantage of the SerDes ports offered on many of the high performance FPGAs, freeing up general purpose I/O for other functions. The disadvantage is that the current mode logic drivers on the ADC consume significantly more current than LVDS drivers. There also must be enough SerDes ports available to accommodate all the ADC interfaces.
Advantages over Typical 6-Wire Serial Transmission
The 8B/10B encoded data is friendly to clock recovery circuits because it is run-length limited. It also accommodates AC coupling because it is DC balanced. 8B/10B encoding involves transforming an 8-bit octet into a 10-bit code group.
In each code group the difference between the number of ones and zeros is never more than two. By monitoring the number of ones and zeros in consecutive code groups, a running disparity is calculated. The transmitter and receiver use this disparity to encode and decode the data.
For each input octet, there are two possible 10-bit output codes. The selection of the code to be transmitted is dependent on the running disparity, and is intended to keep the average number of ones and zeros equal. This property of 8B/10B encoding ensures the DC offset of the signal to be zero. Once the data is encoded, it is serialized and transmitted beginning with bit zero of the first code group.
The JESD204 specification requires that the first code group corresponds with the most significant byte of data. The second code group corresponds with the least significant byte of data. Combined, these two code groups make up one frame of data which constitutes one sample. A 16-bit ADC would be coded into two 10-bit code groups, and then multiplied by the sample rate to determine the bit rate of the 2-wire serial data stream. The 16-bit 105Msps LTC2274, after encoding, produces a serial stream of data transmitted at 2.1Gbps. At this speed, 8B/10B encoding and its unique properties make it possible to reliably transmit serial data over a 2-wire interface.
The JESD204 serial interface make perfect sense for cost sensitive applications where FPGA pin count dominates the cost of the design. Multichannel applications such as medical imaging will benefit from the reduced pin count for ease of routing and additional space savings.
Conclusion
The choice between serial LVDS and JESD204 interface standards will depend on power consumption requirements and availability of SerDes ports on the FPGA. Serial LVDS is perfect for multichannel ADCs with sample rates of up to 125Msps and resolutions of up to 16-bits, with portability in mind.
About the author
Alison Steer is Product Marketing Manager at Linear Technology Corp.
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